Difference between revisions of "High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging"
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[[File: Continuous Time Delta-Sigma Converter Breems.png|thumb|400px]] | [[File: Continuous Time Delta-Sigma Converter Breems.png|thumb|400px]] | ||
==Short Description== | ==Short Description== | ||
− | + | Delta-sigma based converters have been the topology of choice for many high performance applications such a medical imaging since several years due to their high dynamic range and high linearity. More recently the main implementation technique has changed from discrete-time switched capacitor to continuous-time, RC based structures, because they offer implicit filtering, do not need as much buffering in front and can be realized with less power consumption. In this thesis a continuous-time delta-sigma modulator for up to 5MHz bandwidth and 80dB SNDR will be investigated first at behavioral level, followed by a circuit design in 130nm CMOS. It will be possible to learn the whole the design cycle including system simulation and layout as a master student. | |
===Status: Available === | ===Status: Available === | ||
− | : Looking for 1-2 | + | : Looking for 1-2 Master students |
: Contact: [[:User:Burger | Thomas Burger]] | : Contact: [[:User:Burger | Thomas Burger]] | ||
===Prerequisites=== | ===Prerequisites=== | ||
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[[#top|↑ top]] | [[#top|↑ top]] | ||
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==Detailed Task Description== | ==Detailed Task Description== | ||
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[[Category:Available]] | [[Category:Available]] | ||
[[Category:Master Thesis]] | [[Category:Master Thesis]] | ||
− | [[Category: | + | [[Category:Analog IC Design]] |
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[[#top|↑ top]] | [[#top|↑ top]] | ||
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Revision as of 17:13, 4 December 2018
Contents
Short Description
Delta-sigma based converters have been the topology of choice for many high performance applications such a medical imaging since several years due to their high dynamic range and high linearity. More recently the main implementation technique has changed from discrete-time switched capacitor to continuous-time, RC based structures, because they offer implicit filtering, do not need as much buffering in front and can be realized with less power consumption. In this thesis a continuous-time delta-sigma modulator for up to 5MHz bandwidth and 80dB SNDR will be investigated first at behavioral level, followed by a circuit design in 130nm CMOS. It will be possible to learn the whole the design cycle including system simulation and layout as a master student.
Status: Available
- Looking for 1-2 Master students
- Contact: Thomas Burger
Prerequisites
- AIC
Character
- 30% Theory
- 20% System Simulation (Matlab/Simulink)
- 50% Circuit Design