View source for Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator

[[File:Leveling Loop for Very-Low-Distortion Oscillator.jpg|440px|thumb]]
==Short Description==
A key quality parameter of audio signal paths is their distortion performance. For distortion measurements, an oscillator with very low harmonic content (i.e. itself has very low distortion) and noise is necessary. For state-of-the-art resolution, fully analog RC oscillators are required. To stabilize their amplitude, a leveling loop consisting of level detector, error integrator and a multiplier is employed. Implementation of this leveling loop is critical to oscillator performance (e.g. it affects harmonic distortion, settling time and sideband noise) and poses several demanding tradeoffs. This semester thesis investigates a hybride implementation, where the signal path of the leveling loop comprises an AD converter and a multiplying DA converter, with intermediate digital signal processing (FPGA or DSP). Carried out with an industry partner (Weiss Engineering Ltd.).
===Status: Available ===
: Looking for 1-2 Semester students
: Contact: [[:User:felber | Norbert Felber]]
===Prerequisites===
: Interest in high-performance mixed signal circuit design;
: Background in hardware design and low-level sofware implementation (e.g. VHDL or assembler) beneficial
===Character===
: 70% Hardware Implementation
: 30% Software Implementation

===Professor===
: [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin]

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==Detailed Task Description==

===Goals===
===Practical Details===
* '''[[Project Plan]]'''
* '''[[Project Meetings]]'''
* '''[[Design Review]]'''
* '''[[Coding Guidelines]]'''
* '''[[Final Report]]'''
* '''[[Final Presentation]]'''

==Results== 

==Links== 

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[[Category:Digital]]
[[Category:Available]]
[[Category:Semester Thesis]]
[[Category:Audio]]
[[Category:Felber]]

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