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===Useful Reading===
===Useful Reading===
*[ Memory devices and applications for in-memory computing]
*[ Memory devices and applications for in-memory computing]
*[ Deep learning acceleration based on in-memory computing]

Revision as of 12:02, 17 November 2020

IBM ZRLab.png

Short Description

Today, we are entering the era of cognitive computing, which holds great promise in deriving intelligence and knowledge from huge volumes of data. In today’s computers based on von Neumann architecture, huge amounts of data need to be shuttled back and forth at high speeds, a task at which this architecture is inefficient.

It is becoming increasingly clear that to build efficient cognitive computers, we need to transition to non-von Neumann architectures in which memory and processing coexist in some form. At IBM Research–Zurich in the Neuromorphic and In-memory Computing Group, we explore various such computing paradigms from in-memory computing to brain-inspired neuromorphic computing. Our research spans from devices and architectures to algorithms and applications.

About the IBM Research–Zurich

The location in Zurich is one of IBM’s 12 global research labs. IBM has maintained a research laboratory in Switzerland since 1956. As the first European branch of IBM Research, the mission of the Zurich Lab, in addition to pursuing cutting-edge research for tomorrow’s information technology, is to cultivate close relationships with academic and industrial partners, be one of the premier places to work for world-class researchers, to promote women in IT and science, and to help drive Europe’s innovation agenda. Download factsheet

Hyperdimensional Computing (HDC)


Hyperdimensional computing (HDC) is a brain-inspired computing paradigm based on representing information with hypervectors with dimensions in the thousands. Hypervectors are holographic and (pseudo)random with independent and identically distributed (i.i.d.) components. Principles of HDC allow implementing efficient machine learning models, where it has shown few-shot learning capabilities by requiring less training data than conventional machine learning models to do accurate predictions. By its very nature, HDC is extremely robust against failures, defects, variations, and noise, all of which are complementary to ultra-low energy computation on nanoscale fabrics such as Phase-Change Memory (PCM) devices.  By eliminating non von-Neumann bottleneck, PCM-based in-memory computing systems enable building systems that can run HDC models at very high energy efficiencies. This opens doors to a vast spectrum of further research in applications, algorithms, architecture and system development.

HDC has also been successfully applied in few-shot meta-learning problems - where a controller is trained to distinguish previously unseen classes by feeding only a few examples. The state-of-the-art accuracy in few-shot learning problems has been achieved by augmenting the controller with an explicit memory and guiding the controller to learning HDC representations. Exciting further research awaiting in this direction includes exploring compact representation of explicit memory and exploring novel cost functions and training algorithms to further improving the classification accuracy.

Useful Reading


  • Python
  • Background in machine learning (recommended)
  • Experience with any deep learning framework such as TensorFlow or PyTorch (recommended)
  • VLSI I and VLSI II (recommended)

In-Memory Computing (IMC)

For decades, conventional computers based on the von Neumann architecture have performed computation by repeatedly transferring data between their processing and their memory units, which are physically separated. As computation becomes increasingly data-centric and as the scalability limits in terms of performance and power are being reached, alternative computing paradigms are searched for in which computation and storage are collocated. A fascinating new approach is that of computational memory where the physics of nanoscale memory devices are used to perform certain computational tasks within the memory unit in a non-von Neumann manner. Computational Memory (CM) is finding application in a variety of areas such as machine learning and signal processing. In addition to novel non-volatile memory technologies like PCM and ReRAM, also conventional SRAM has been proposed as underlying storage technology in Computational Memories.

Useful Reading


  • General interest in Deep Learning and memory/system design
  • VLSI I and VLSI II (recommended)
  • Analog Circuit Design (recommended)

Specific requirements for the different projects vary and are generally negotiable.

Available Projects

We are inviting applications from students to conduct their master’s thesis work or an internship project at the IBM Research lab in Zurich on this exciting new topic.

Type Project Description Topic Workload Type
MA Lifelong learning challenge Artificial general intelligence (AGI): lifelong learning challenge HDC algorithmic design
MA Machine learning based on optimal transport using in-memory computing' Machine learning based on optimal transport using in-memory computing HDC algorithmic design
MA Developing Efficient Models of Strong AI for Intelligence Quotient (IQ) Test Developing Efficient Models of Strong AI for Intelligence Quotient (IQ) Test HDC algorithmic design
MA Accurate deep learning inference using computational memory Project description and application IMC algorithmic design
MA ADC design for computational memory Digital-to-Analog converters (DACs) and Analog-to-Digital converters (ADCs) are extensively employed in Computational Memory (CM) to handle the crossing between the digital and analog domain, in which computationally expensive tasks, like Matrix-Vector Multiplications (MVM), are carried out with O(1) complexity. Each conversion costs a certain amount of energy and its precision can only be guaranteed up to the Effective Number of Bits (ENOB) of the employed data converter.
The research focus will be on understanding the system level requirements on ADC and DAC for optimal performance of Deep Neural Network inference using CM. Furthermore, the effects of noise, non-linearity and manufacturing tolerances shall be examined and counter measurements, like for example periodic digital ADC recalibration and digital post processing, shall be evaluated with regards to effectivity and energy costs.
IMC analog circuit design
SA Testing of a computational memory chip This project is about building a Microprocessor/FPGA-based test platform around a novel IMC chip. After commissioning the chip, DL workload tests can be run to characterize its throughput and energy-efficiency. IMC PCB Design
µ-code implementation
MA/SA Neural Network Training on a
computational memory chip
TBA IMC algorithm/system design
analog circuit design


Thesis will be at IBM Zurich in Rüschlikon
Hyperdimensional Computing (HDC) projects
Contact (at ETH Zurich): Dr. Frank K. Gurkaynak and Michael Hersche
Contact (at IBM): Dr. Abu Sebastian
Contact (at IBM): Dr. Abbas Rahimi
Professor: Luca Benini
In-Memory Computing (IMC) projects
Contact (at IBM/ETH Zurich): Riduan Khaddam-Aljameh
Contact (at IBM): Dr. Abu Sebastian
Professor: Luca Benini