Difference between revisions of "IBM Research"

Revision as of 02:26, 11 November 2020

Short Description

Today, we are entering the era of cognitive computing, which holds great promise in deriving intelligence and knowledge from huge volumes of data. In today’s computers based on von Neumann architecture, huge amounts of data need to be shuttled back and forth at high speeds, a task at which this architecture is inefficient.

It is becoming increasingly clear that to build efficient cognitive computers, we need to transition to non-von Neumann architectures in which memory and processing coexist in some form. At IBM Research–Zurich in the Neuromorphic and In-memory Computing Group, we explore various such computing paradigms from in-memory computing to brain-inspired neuromorphic computing. Our research spans from devices and architectures to algorithms and applications. Here is a list of available projects:

About the IBM Research–Zurich

The location in Zurich is one of IBM’s 12 global research labs. IBM has maintained a research laboratory in Switzerland since 1956. As the first European branch of IBM Research, the mission of the Zurich Lab, in addition to pursuing cutting-edge research for tomorrow’s information technology, is to cultivate close relationships with academic and industrial partners, be one of the premier places to work for world-class researchers, to promote women in IT and science, and to help drive Europe’s innovation agenda. Download factsheet

HD Computing

In-Memory Computing (IMC)

For decades, conventional computers based on the von Neumann architecture have performed computation by repeatedly transferring data between their processing and their memory units, which are physically separated. As computation becomes increasingly data-centric and as the scalability limits in terms of performance and power are being reached, alternative computing paradigms are searched for in which computation and storage are collocated. A fascinating new approach is that of computational memory where the physics of nanoscale memory devices are used to perform certain computational tasks within the memory unit in a non-von Neumann manner. Computational Memory (CM) is finding application in a variety of areas such as machine learning and signal processing. In addition to novel non-volatile memory technologies like PCM and ReRAM, also conventional SRAM has been proposed as underlying storage technology in Computational Memories.

Prerequisites

General interest in Deep Learning and memory/system design
VLSI I and VLSI II (recommended)
Analog Circuit Design (recommended)

Specific requirements for the different projects vary and are generally negotiable.

Available Projects

Type	Project	Description	Topic	Workload Type
SA	Testing of a computational memory chip	TBA	IMC	PCB Design and/or µ-code implementation
MA/SA	Neural Network Training on a computational memory chip	TBA	IMC	algorithm/system design and/or analog circuit design
MA	ADC design for computational memory	Digital-to-Analog converters (DACs) and Analog-to-Digital converters (ADCs) are extensively employed in Computational Memory (CM) to handle the crossing between the digital and analog domain, in which computationally expensive tasks, like Matrix-Vector Multiplications (MVM), are carried out with O(1) complexity. Each conversion costs a certain amount of energy and its precision can only be guaranteed up to the Effective Number of Bits (ENOB) of the employed data converter. The research focus will be on understanding the system level requirements on ADC and DAC for optimal performance of Deep Neural Network inference using CM. Furthermore, the effects of noise, non-linearity and manufacturing tolerances shall be examined and counter measurements, like for example periodic digital ADC recalibration and digital post processing, shall be evaluated with regards to effectivity and energy costs.	IMC	analog circuit design

Contact

Thesis will be at IBM Zurich in Rüschlikon
HD Computing projects: Contact (at ETH Zurich): Dr. Frank K. Gurkaynak and Michael Hersche; Contact (at IBM): Dr. Abu Sebastian; Contact (at IBM): Dr. Abbas Rahimi; Professor: Luca Benini
In-Memory Computing (IMC) projects: Contact (at IBM/ETH Zurich): Riduan Khaddam-Aljameh; Contact (at IBM): Dr. Abu Sebastian; Professor: Luca Benini

@@ Line 20: / Line 20: @@
-===Status: Available===
+==HD Computing==
-: Looking for 2 Master students
+==In-Memory Computing (IMC)==
+For decades, conventional computers based on the von Neumann architecture have performed computation by repeatedly transferring data between their processing and their memory units, which are physically separated. As computation becomes increasingly data-centric and as the scalability limits in terms of performance and power are being reached, alternative computing paradigms are searched for in which computation and storage are collocated. A fascinating new approach is that of computational memory where the physics of nanoscale memory devices are used to perform certain computational tasks within the memory unit in a non-von Neumann manner. '''Computational Memory''' (CM) is finding application in a variety of areas such as machine learning and signal processing. In addition to novel non-volatile memory technologies like '''PCM''' and '''ReRAM''', also conventional '''SRAM''' has been proposed as underlying storage technology in Computational Memories.
+===Prerequisites===
+*General interest in Deep Learning and memory/system design
+*VLSI I and VLSI II (''recommended'')
+*Analog Circuit Design (''recommended'')
+Specific requirements for the different projects vary and are generally negotiable.
+==Available Projects==
+{| class="wikitable" style="text-align: center;"
+|-
+! style="width: 5%;"|Type !! style="width: 20%"|Project !! style="width: 60%"|Description !! style="width: 5%"|Topic !! style="width: 15%"|Workload Type
+|-
+| SA || Testing of a computational memory chip || style="text-align: justify;"|TBA || IMC || PCB Design <br /> and/or<br />  µ-code implementation
+|-
+| MA/SA || Neural Network Training on a <br /> computational memory chip || style="text-align: justify;"|TBA || IMC || algorithm/system design<br />and/or<br />  analog circuit design
+|-
+| MA || ADC design for computational memory || style="text-align: justify;"|Digital-to-Analog converters ('''DAC'''s) and Analog-to-Digital converters ('''ADC'''s) are extensively employed in Computational Memory ('''CM''')  to handle the crossing between the digital and analog domain, in which computationally expensive tasks, like Matrix-Vector Multiplications ('''MVM'''), are carried out with O(1) complexity. Each conversion costs a certain amount of energy and its precision can only be guaranteed up to the Effective Number of Bits ('''ENOB''') of the employed data converter. <br /> The research focus will be on understanding the system level requirements on ADC and DAC for optimal performance of Deep Neural Network inference using CM. Furthermore, the effects of noise, non-linearity and manufacturing tolerances shall be examined and counter measurements, like for example periodic digital ADC recalibration and digital post processing, shall be evaluated with regards to effectivity and energy costs.|| IMC || analog circuit design
+|}
+==Contact==
 : Thesis will be at IBM Zurich in Rüschlikon
+; HD Computing projects
 : Contact (at ETH Zurich): [[:User:kgf | Dr. Frank K. Gurkaynak]] and [[:User:Herschmi | Michael Hersche]]
 : Contact (at IBM): [mailto:ase@zurich.ibm.com Dr. Abu Sebastian]
 : Contact (at IBM): [mailto:abr@zurich.ibm.com Dr. Abbas Rahimi]
+: Professor: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]
-===Professor===
+; In-Memory Computing (IMC) projects
-: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]
+: Contact (at IBM/ETH Zurich): [[:User:rid | Riduan Khaddam-Aljameh]]
+: Contact (at IBM): [mailto:ase@zurich.ibm.com Dr. Abu Sebastian]
+: Professor: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]

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