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Ibex: Bit-Manipulation Extension

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Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture. It is open source, has originally been designed at ETH Zürich and University of Bologna under the name Zero-riscy [1], and has been taped out multiple times in a mix of academic and industry projects. Since December 2018, Ibex is actively maintained and developed by the not-for-profit company lowRISC C.I.C.. Besides making the design fully compliant to the RISC-V specification, cleaning up the codebase, documenting the design, adding new features such as support for U-Mode and PMP, considerable effort has been put into establishing industry-level verification infrastructure.

Today, Ibex is a high-quality open-source design that is flexible (It offers multiple configuration options such optional support for RISC-V E- and M- extensions, different multiplier implementations), yet simple. It is used for projects in industry and academia, as well as for teaching purposes, and by hobbyists. However, the simplicity currently comes at the price of lower performance in terms of cycles per instruction compared to bigger cores such as RI5CY [1]. On one hand the performance of Ibex is lower due to the simpler pipeline design, on the other hand it is due to the fact that Ibex does not implement RISC-V instruction set extensions beyond M and C (E can optionally be enabled but is not beneficial for performance).

Short Description

The goal of this project is to improve the performance of Ibex in micro-controller-type workloads by adding support for the RISC-V bit-manipulation, or short B, instruction-set extension. To this end, you will:

  • Do a design-space exploration for adding support for the current draft of the B extension to Ibex.
  • Make a decision on which subsets of the B extension are most beneficial for Ibex and workloads typical for such embedded micro-controller cores.
  • Find a middle ground between area and performance for the selected subset and provide a high-quality reference implementation as well as tests.

Status: Available

Looking for 1-2 Interested Master Students (Semester Project)
Supervision: Pirmin Vogel, Pasquale Davide Schiavone


20% Theory, computer architecture
60% Design space exploration: RTL design, simulation, benchmarking
20% Verification


Basics in VLSI design (VLSI1 course), SystemVerilog, computer architecture
Experience with using the GNU Compiler Collection (GCC) or LLVM+Clang is beneficial
Motivation to work hard on a cool open-source project


Luca Benini


  1. P.D. Schiavone, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications", Proceedings of the 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki, Greece, 2017. link

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