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Ibex: FPGA Optimizations

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Intro

Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture. It is open source, has originally been designed at ETH Zürich and University of Bologna under the name Zero-riscy, and has been taped out multiple times in a mix of academic and industry projects. Since December 2018, Ibex is actively maintained and developed by the not-for-profit company lowRISC C.I.C.. Besides making the design fully compliant to the RISC-V specification, cleaning up the codebase, documenting the design, adding new features such as support for U-Mode and PMP, considerable effort has been put into establishing industry-level verification infrastructure.

Today, Ibex is a high-quality open-source design that is used for projects in industry and academia, as well as for teaching purposes, and by hobbyists. The design is simple, yet flexible: It offers multiple configuration options (optional support for RISC-V E- and M- extensions, different multiplier implementations) and can be used in both ASIC and FPGA designs. However, it primarily targets ASIC designs and is optimized for low area footprint and energy consumption in ASIC technologies. On FPGAs, Ibex currently has a higher resource utilization and achieves lower clock frequencies than FPGA-only cores of comparable performance such as Xilinx MicroBlaze.

Short Description

The goal of this project is to:

  1. Explore possibilities for improving the resource utilization and achievable clock frequency of Ibex on FPGA targets.
  2. Find a middle ground between optimizing Ibex for FPGA targets and keeping the codebase generic.

To get started, the following things should be investigated:

  • Come up with a the register file implementation that leverages RAM32M primitives or similar instead of FFs.
  • Modify the ALU and add a new single-cycle multiplier to make use of DSP slices. This should also have a positive effect on performance in terms of cycles per instruction.
  • Investigate the control and status registers including performance monitors. These take up a lot of resources and are currently not mapped efficiently to the FPGA logic.

As you familiarize with the codebase and the optimization for FPGA targets, other

Status: Available

Looking for 1 Interested Master Student (Semester Project)
Supervision: Pirmin Vogel, Pasquale Davide Schiavone

Character

30% Theory, computer architecture
40% FPGA optimization at RTL
30% Simulation, verification, benchmarking

Prerequisites

Basics in VLSI design (VLSI1 course), SystemVerilog, computer architecture
Experience with FPGA design is helpful but not required
Motivation to work hard on a cool open-source project

Professor

Luca Benini

References

  1. P.D. Schiavone, et al. "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications", Proceedings of the 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki, Greece, 2017. link

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