View source for Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)

[[Category:Digital]]
[[Category:High Performance SoCs]]
[[Category:Computer Architecture]]
[[Category:2020]]
[[Category:Semester Thesis]]
[[Category:Tbenz]]
[[Category:Paulsc]]
[[Category:Nwistoff]]
[[Category:Available]]

IBM recently contributed their A2O processor core to the open-source community. The A2O is a 2-way multithreaded out-of-order core optimized for single thread performance. It is completely written in Verilog 2001. 

Even though the A2O is primarily targeted for embedded applications, it features high computational throughput by running up to 3GHz in a 45nm technology node. It was created as an application-grade linux-capable processor to be integrated in large SoCs primarily targeting applications like Artificial Intelligence and Autonomous driving. 

For us at IIS the core poses a great opportunity to advance from rather simple pipelined in-order cores (RI5CY, Zero-riscy, Ariane) to a full-fledged commercial superscalar, multi-threaded, out-of-order processor. There are many knobs available in RTL to tune and tweak the A2O core. As of now, only a single configuration has been tested and successfully implemented on an FPGA. There are therefore plenty of opportunities to experiment with the parameters and investigate their impact on performance, area, and speed.

== Thesis Content ==
The thesis will be divided into the following sub tasks:

* '''Initial exploration:''' get familiar and understand the structure of the A2O core
* '''RTL synthesis:''' process the Verilog source of the A2O core to be compatible with our synthesis toolchain and synthesize the default configuration
* '''RTL simulation:''' understand the interface of the core and create a testbench that can execute binaries on the processor
* '''Parameter exploration:''' understand what parameters can be tweaked and how they influence performance, area, and speed in a 22nm node.

== Requirements ==

* Profound knowledge of computer architecture
* Experience with HDLs such as taught in ''VLSI I''
* Preferably previous experience with FPGAs and / or an ASIC toolflow (simulation & synthesis)

Composition: 40% initial exploration and base-line synthesis, 30% RTL simulation, 40% parameter exploration

== Further Reading ==
* [https://github.com/openpower-cores/a2o A2O on GitHub]

== Project Supervisors ==
* [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]
* [[:User:Paulsc | Paul Scheffler]]: [mailto:paulsc@iis.ee.ethz.ch paulsc@iis.ee.ethz.ch]
* [[:User:Nwistoff | Nils Wistoff]]: [mailto:nwistoff@iis.ee.ethz.ch nwistoff@iis.ee.ethz.ch]