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Revision as of 15:43, 5 February 2015

Low-power chip-to-chip communication network.jpg

Short Description

As individual chips grow in complexity and capability, their I/O requirements also contuinue to increase. It is a significant challenge to provide the necessary I/O bandwidth in modern chips. Current solutions center on fast serial differential I/O which are able to transfer data at multiple Gbits/s.

Most off-chip communication is assumed to be long-distance and typical I/O drivers are designed to drive large capacitive loads over, comparatively long distances. Recent 2.5D and 3D integration practices, face the same challenges, however they need to cover significantly shorter distances (typically from 0.1mm to 10mm) as dies are either placed on top of each other (3D) or stacked in a way to enable bonding pads to connect different layers (2.5D).

The goal of the project is to develop a communication network that is able to transfer data with the least possible power consumption over such connections. In this project, you will get a clear understanding on how to architect and design embedded heterogeneous computer systems in nano-meter technology. You will be exposed to state-of-the-art and upcoming technologies such as ultra-thin body SOI, FINFETs and three-dimensional integration.

Status: Available

Looking for 1-2 Semester/Master students
Contact: Frank K. Gurkaynak

Prerequisites

VLSI I
VLSI II (recommended)

Character

25% Theory
25% ASIC Design
50% EDA tools

Professor

Luca Benini

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