Matheus Cavalcante
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Matheus Cavalcante
- e-mail: matheusd@iis.ee.ethz.ch
I received my M.Sc. in integrated electronic systems from the Grenoble INP (Phelma) in 2018. I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Luca Benini.
My current research interests include:
- Computer and System Architecture
- High-Performance Computing
- Vector Processing
- Interconnection Networks
Available Projects
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Fast Simulation of Manycore Systems (1S)
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
Projects In Progress
No pages meet these criteria.
Completed Projects
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Transforming MemPool into a CGRA (M)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Manycore System on FPGA (M/S/G)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- ISA extensions in the Snitch Processor for Signal Processing (M)
- MemPool on HERO (1S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
