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Multi issue OoO Ariane Backend (M)

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Introduction

Ariane/CVA6 (it transitioned to Openhardware in June and was renamed to CVA6, however, we like the name and keep it as an internal code name) is a popular, 6-stage, in-order, RISC-V CPU designed as part of the PULP project and capable of booting Linux. The current Ariane backend [1] is built around a scoreboard (essentially a small ROB) which took over more and more functionality.

A widely employed technique to increase sequential performance (IPC) is to issue multiple instructions per cycle, we call such architectures superscalar. A second performance improvement can come from the fact that not all instructions depend on each other. Clever architecture can issue independent instructions out of program order, exploiting instruction-level parallelism (ILP).

But increasing the issue width would mean adding further ports into the scoreboard, increasing complexity, power, and reducing operating frequency.

Project

This project proposes to re-architect the backend of Ariane (keeping the frontend and caches as well as suitable sub-blocks such as TLBs, FPU, etc.) in a similar manner as other OoO architectures such as the MIPS R10000 [2], Alpha 21264 [3], OpenPower A20 [4], Boom [5]. Ideally, we would make the core parametric over the issue width (ranging from single issue up to four or six-way superscalar). The final goal is to have a reasonably advanced superscalar core running at around 1.5GHz operating frequency in a modern 12nm process with IPCs expected from that class of processor [6].

Depending on the timeframe further features can be added:

  • RoCC Interface
  • Bitmanipulation ALU
  • Multi-level TLBs
  • Page walk cache
  • Speculative load/store disambiguation predictor [7]

This is an ambitious (but super rewarding) project so we are preferably looking for very dedicated master thesis students. In case you should be interested as part of a semester thesis we can try to find a suitable subset (for example just the re-naming logic) on which you can work.

Requirements
  • Strong interest in computer architecture
  • Experience with HDLs (preferably SystemVerliog) such as taught in VLSI I
  • Knowledge of ASIC tool flow (Synthesis) or parallel enrollment with VLSI II

Composition: 30% Architecture specification, 40% Verification, 30% RTL Implementation

Project Supervisors


References