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Difference between revisions of "Optimal System Duty Cycling for a Mobile Health Platform"

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[[File:pg_tradeoff.png|400px|thumb|right|Basic tradeoff mechanism between power- and clock gating.]]
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[[File:pg_tradeoff.png|400px|thumb|right|Basic tradeoff mechanism between clock- (left) and power gating (right).]]
  
 
To meet the power requirements of wearable and implantable devices, duty cycling of unused components is a crucial mechanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level duty cycling of the PULP processing subsystem on our main ASIC VivoSoC.
 
To meet the power requirements of wearable and implantable devices, duty cycling of unused components is a crucial mechanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level duty cycling of the PULP processing subsystem on our main ASIC VivoSoC.

Revision as of 12:55, 23 May 2018

Basic tradeoff mechanism between clock- (left) and power gating (right).

To meet the power requirements of wearable and implantable devices, duty cycling of unused components is a crucial mechanism both for sub-systems on the chip level as well as components on the system level, e.g. flash memory or radio ICs. This project focuses on chip-level duty cycling of the PULP processing subsystem on our main ASIC VivoSoC.

As in every clocked digital circuit, the power consumption consists of leakage power that depends on the supply voltage and dynamic power which depends linearly on the operation frequency and quadratically on the supply voltage. By disabling the clock signal on idle parts of a circuit (called clock gating), the dynamic power can be eliminated and operation of the circuit quickly restored when needed. Also, the circuit overhead to enable clock gating is very small and hence fine-grain duty cycling is achievable. However, the leakage power continues to be consumed during idle periods, leading to wasted energy (see figure on the right).

To overcome this limitation, the concept of power gating allows to switch off the supply voltage of unused circuit partitions, eliminating any power consumption. Besides significantly higher design overhead, the major drawback of power- compared to clock gating is the loss of the state of the circuit (value of all sequential/storing elements). To continue operation after an idle period, the state prior to the idle period must first be restored. In processing systems like PULP this translates mostly to a reboot of the processing cores, making them ready for further computations. Naturally, this process consumes parasitic energy, labeled Ereboot in the figure.

In this thesis you will learn:


Status: Available

We are looking for 1-2 motivated Semester Thesis students
Contact: Florian Glaser

Prerequisites

  • Some experience with embedded/low level software
  • Interest in embedded systems and uControllers


Character

  • 20% Concept
  • 40% Embedded software design
  • 40% Experiments/Measurements