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===Related Available Projects===
 
===Related Available Projects===
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<DynamicPageList>
 
<DynamicPageList>
 
category = PULP
 
category = PULP
 
category = Available
 
category = Available
 
</DynamicPageList>
 
</DynamicPageList>
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=== [http://asic.ethz.ch/cg/applications/Pulp.html Related Chips] ===
 
=== [http://asic.ethz.ch/cg/applications/Pulp.html Related Chips] ===
 
====28nm====
 
====28nm====
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* [http://asic.ethz.ch/2015/Diego.html Diego] Large PULP chip with in-exact accelerators, LVT version  
 
* [http://asic.ethz.ch/2015/Diego.html Diego] Large PULP chip with in-exact accelerators, LVT version  
 
* [http://asic.ethz.ch/2015/Manny.html Manny] Large PULP chip with in-exact accelerators, sub-threshold version
 
* [http://asic.ethz.ch/2015/Manny.html Manny] Large PULP chip with in-exact accelerators, sub-threshold version
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===Publications===
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====2016====
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* ''High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme'', Y. Popoff, F. Scheidegger, M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, DATE, 2016
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* ''A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster'', M. Gautschi, M. Schaffner, F. K. Gürkaynak, L. Benini, ISSCC, 2016
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====2015====
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* ''A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters'', F. Conti, L. Benini, DATE, 2015, [http://dl.acm.org/citation.cfm?id=2755753.2755910 paper]
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* ''Exploring Multi-banked Shared-L1 Program Cache on Ultra-Low Power Tightly Coupled Processor Clusters'', I. Loi, D. Rossi, G. Haugou, M. Gautschi, L. Benini, ACM Computing Frontiers, 2015, [http://dx.doi.org/10.1145/2742854.2747288 paper]
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* ''A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, I. Loi, F. K. Gürkaynak, A. Bartolini, P. Flatresse, L. Benini, Solid-State Electronics, 2016, [http://dx.doi.org/10.1016/j.sse.2015.11.015 paper]
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* ''PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications'', D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, L. Benini, HOT Chips, 2015, [http://www.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.10-IoT-Epub/HC27.24.111-PULP-Rossi-DEL-ETH-2.pdf slides]
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* ''Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores'', M. Gautschi, A. Traber, A. Pullini, L. Benini, M. Scandale, A. Di Federico, M. Beretta, G. Agosta, VLSI-SoC, 2015, [http://dx.doi.org/10.1109/VLSI-SoC.2015.7314386 paper]
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====2014====
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* ''Energy-efficient vision on the PULP platform for ultra-low power parallel computing'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, SiPS, 2014, [http://dx.doi.org/10.1109/SiPS.2014.6986099 paper]
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* ''Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters'', D. Rossi, I. Loi, G. Haugou, L. Benini, ACM Computing Frontiers, 2014, [http://dx.doi.org/10.1145/2597917.2597922 paper]
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* ''Customizing an Open Source Processor to Fit in an Ultra-Low Power Cluster with a Shared L1 Memory'', M. Gautschi, D. Rossi, L. Benini, GLSVLSI, 2014, [http://dx.doi.org/10.1145/2591513.2591569 paper]
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 +
* ''Energy efficient parallel computing on the PULP platform with support for OpenMP'', D. Rossi, I. Loi, F. Conti, G. Tagliavini, A. Pullini, A. Marongiu, IEEEI, 2014, [http://dx.doi.org/10.1109/EEEI.2014.7005803 paper]
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===Links===
 
===Links===
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** [http://compilergroup-srv.elet.polimi.it/toolchains/or1k-toolchain-linux-amd64-latest.tar.gz Latest compiled toolchain for Linux EL6]
 
** [http://compilergroup-srv.elet.polimi.it/toolchains/or1k-toolchain-linux-amd64-latest.tar.gz Latest compiled toolchain for Linux EL6]
  
===[http://www-micrel.deis.unibo.it/pulp-project/literature Publications]===
 
For an up to date list of papers please see the [http://www-micrel.deis.unibo.it/pulp-project/literature Literature] link of the [http://www-micrel.deis.unibo.it/pulp-project PULP page in University of Bologna].
 
  
 
===Logos===
 
===Logos===

Revision as of 15:02, 28 January 2016


PULP logo (for different variants and file formats see below)

PULP - an Open Parallel Ultra-Low-Power Processing-Platform

Basic block diagram of a PULP system

This is a joint project between the Integrated Systems laboratory (IIS) of ETH Zurich (IIS) and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.

The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.

Inquiries from interested partners are welcome.

....more to follow.... stay tuned!

Related Available Projects


Related Chips

28nm

  • Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
  • Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
  • Pulp v3 The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
  • Honey Bunny PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.

65nm

  • Mia Wallace Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 Kbyte memory (65nm)
  • Artemis 4 core PULP system including FPU (65nm).
  • Hecate 4 core PULP system with 2 shared FPUs (65nm).
  • Selene 4 core PULP system with 1 shared FPU using a logarithmic number system (65nm).
  • Diana 4 core PULP system with FPUs designed using approximate computing techniques (65nm).
  • Phoebe an improved version of Selene, 4 cores and 1 shared vectoral FPU using logarithmic number system
  • Imperio single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project.

130nm

  • Vivosoc 2 core mixed-signal PULP system with a low-power A/D converter (130nm)

180nm

  • Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP.
  • Sir10us A cryptographic application that uses the Or10n processor developed for PULP.
  • Sid Large PULP chip with in-exact accelerators, LL version
  • Diego Large PULP chip with in-exact accelerators, LVT version
  • Manny Large PULP chip with in-exact accelerators, sub-threshold version


Publications

2016

  • High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme, Y. Popoff, F. Scheidegger, M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, DATE, 2016
  • A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster, M. Gautschi, M. Schaffner, F. K. Gürkaynak, L. Benini, ISSCC, 2016

2015

  • A ultra-low-energy convolution engine for fast brain-inspired vision in multicore clusters, F. Conti, L. Benini, DATE, 2015, paper
  • Exploring Multi-banked Shared-L1 Program Cache on Ultra-Low Power Tightly Coupled Processor Clusters, I. Loi, D. Rossi, G. Haugou, M. Gautschi, L. Benini, ACM Computing Frontiers, 2015, paper
  • A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology, D. Rossi, A. Pullini, I. Loi, F. K. Gürkaynak, A. Bartolini, P. Flatresse, L. Benini, Solid-State Electronics, 2016, paper
  • PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications, D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, L. Benini, HOT Chips, 2015, slides
  • Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores, M. Gautschi, A. Traber, A. Pullini, L. Benini, M. Scandale, A. Di Federico, M. Beretta, G. Agosta, VLSI-SoC, 2015, paper

2014

  • Energy-efficient vision on the PULP platform for ultra-low power parallel computing, F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, SiPS, 2014, paper
  • Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters, D. Rossi, I. Loi, G. Haugou, L. Benini, ACM Computing Frontiers, 2014, paper
  • Customizing an Open Source Processor to Fit in an Ultra-Low Power Cluster with a Shared L1 Memory, M. Gautschi, D. Rossi, L. Benini, GLSVLSI, 2014, paper
  • Energy efficient parallel computing on the PULP platform with support for OpenMP, D. Rossi, I. Loi, F. Conti, G. Tagliavini, A. Pullini, A. Marongiu, IEEEI, 2014, paper


Links


Logos

This archive contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.

Inline

Inline PULP logo, variant 2 (PNG PDF). Inline PULP logo, variant 1 (PNG PDF).

Small

Big PULP logo, variant 2 (PNG PDF). Big PULP logo, variant 1 (PNG PDF). Main PULP logo icon (PNG PDF).