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[[File:pulp_v3_sml.jpg | thumb | 400px | Die micrograph of [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3].]]
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[[File:pulp_v3_sml.jpg | thumb | 400px | Layout of [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3].]]
  
  
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The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet  the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.
 
The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet  the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.
  
 
+
See our '''[http://pulp-platform.org Main Project webpage]''', our [https://github.com/pulp-platform GitHub project page] or follow us on [https://twitter.com/pulp_platform Twitter] for up to date information.  
[mailto:lbenini@iis.ee.ethz.ch Inquiries] from interested partners are welcome.
 
 
 
''....more to follow.... stay tuned!''
 
 
 
See also:
 
* [http://www.pulp-platform.org Official PULP Project Website]
 
* [https://github.com/pulp-platform/pulpino PULPino on GitHub]
 
 
 
 
 
=== PULPino - A Small Single-Core System Based on PULP ===
 
PULPino is an open-source microcontroller like system, based on a small 32-bit
 
RISC-V core that was developed at ETH Zurich. The core has an IPC close to 1, full
 
support for the base integer instruction set (RV32I), compressed instructions
 
(RV32C) and partial support for the multiplication instruction set
 
extension (RV32M). It implements our non-standard extensions for hardware
 
loops, post-incrementing load and store instructions, ALU and MAC
 
operations.
 
To allow embedded operating systems such as FreeRTOS to run, a subset of the
 
privileged specification is supported. When the core is idle, the platform can
 
be put into a low power mode, where only a simple event unit is active and
 
wakes up the core in case an event/interrupt arrives.
 
 
 
The PULPino platform is available for RTL simulation, FPGA and the first ASIC
 
(called [http://asic.ethz.ch/2015/Imperio.html Imperio]) has been taped out in January 2016.
 
It has full debug support on all targets. In addition we support extended profiling with source code
 
annotated execution times through KCacheGrind in RTL simulations.
 
 
 
PULPino is based on IP blocks from the PULP project.
 
 
 
 
 
See also:
 
* [http://www.pulp-platform.org Official PULP Project Website]
 
* [https://github.com/pulp-platform/pulpino PULPino on GitHub]
 
* [http://riscv.org/workshop-jan2016/Wed1315%20PULP%20riscv3_noanim.pdf Slides] / [[Media:pulpino_poster_riscv2015.pdf|poster]] from RISC-V Workshop, 2016.
 
* [https://www.dropbox.com/s/vtrgqnc7dm7gbx2/Andreas%20Traber%20-%20pulpino.pdf?dl=0 Slides] from ORCONF, 2015.
 
  
 
===Related Available Student Projects===
 
===Related Available Student Projects===
 
 
<DynamicPageList>
 
<DynamicPageList>
 
category = PULP
 
category = PULP
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=== [http://asic.ethz.ch/cg/applications/Pulp.html Related Chips] ===
 
=== [http://asic.ethz.ch/cg/applications/Pulp.html Related Chips] ===
 +
====22nm====
 +
* [http://asic.ethz.ch/2018/Poseidon.html Poseidon] A chip containing both PULPissimo (updated single core microcontroller with 32-bit core) and Ariane (64 bit RISC-V core)
 +
* [http://asic.ethz.ch/2018/Kosmodrom.html Kosmodrom] The chip contains two instances of an improved Ariane cores (with FPUs) optimized for different operation corners
 +
* [http://asic.ethz.ch/2018/Arnold.html Arnold] Combines an eFPGA from [http://www.quicklogic.com Quicklogic] and a 32bit PULPissimo system with a RI5CY with FPU support
 +
* [http://asic.ethz.ch/2019/Baikonur.html Baikonur] Two Ariane cores (similar to Kosmodrom) and introducing Bowtruckle a many core system around the Snitch core.
 +
* [http://asic.ethz.ch/2020/Thestral.html Thestral] Snitch based system with 1x cluster (8x compute + 1x DMA core) and 1x governor core. Designed to test fine grained power gating solutions.
 +
 
====28nm====
 
====28nm====
 
* [http://asic.ethz.ch/2013/Pulp.html Pulp v1] The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.  
 
* [http://asic.ethz.ch/2013/Pulp.html Pulp v1] The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.  
Line 64: Line 35:
 
* [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3] The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
 
* [http://asic.ethz.ch/2015/Pulpv3.html Pulp v3] The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
 
* [http://asic.ethz.ch/2015/Honey_Bunny.html Honey Bunny] PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.
 
* [http://asic.ethz.ch/2015/Honey_Bunny.html Honey Bunny] PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.
 +
 +
====40nm====
 +
* [http://asic.ethz.ch/2017/Mr.Wolf.html Mr. Wolf] new generation PULP system with 1 fabric controller (micro-riscy) and a cluster with eight RI5CY (RISC-V cores optimized for DSP operations) and two shared IEEE-754 FPUs.
  
 
====65nm====
 
====65nm====
Line 74: Line 48:
 
* [http://asic.ethz.ch/2015/Phoebe.html Phoebe] an improved version of [http://asic.ethz.ch/2014/Selene.html Selene], 4 cores and 1 shared vectorial FPU using logarithmic number system
 
* [http://asic.ethz.ch/2015/Phoebe.html Phoebe] an improved version of [http://asic.ethz.ch/2014/Selene.html Selene], 4 cores and 1 shared vectorial FPU using logarithmic number system
 
* [http://asic.ethz.ch/2015/Imperio.html Imperio] single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project.  
 
* [http://asic.ethz.ch/2015/Imperio.html Imperio] single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project.  
 +
* [http://asic.ethz.ch/2016/Patronus.html Patronus] chip with three separate single RISC-V cores. It is technically a newer PULPino (single core system)
 +
* [http://asic.ethz.ch/2018/Scarabaeus.html Scarabaeus] a 64-bit system with one Ariane core, peripherals, and a new interrupt controller.
 +
* [http://asic.ethz.ch/2018/Atomario.html Atomario] multi-cluster system with two four-core RI5CY clusters.
 +
* [http://asic.ethz.ch/2019/Billywig.html Billywig] multi-core system with a new Snitch core (RV32IMAFD) with extensions to improve stream processing
 +
* [http://asic.ethz.ch/2019/PLINK.html Plink] Serial I/O interface for PULP
 +
* [http://asic.ethz.ch/2019/Urania.html Urania] BigPULP implementation with one Ariane core and two clusters each with 4x RI5CY cores and a DDR interface
 +
* [http://asic.ethz.ch/2019/Xavier.html Xavier] PULPissimo system with multiple SPI ports, a uDMA with pre-processing capability and a QNE accelerator
 +
* [http://asic.ethz.ch/2019/Rosetta.html Rosetta] PULPissimo system with multiple in-memory computing accelerators.
 +
* [http://asic.ethz.ch/2020/Dustin.html Dustin] PULP cluster with new SIMD extensions.
 +
 
====130nm====
 
====130nm====
* [http://asic.ethz.ch/2015/Vivosoc.html Vivosoc] 2 core mixed-signal PULP system with a low-power A/D converter (130nm)
+
* [http://asic.ethz.ch/2015/Vivosoc.html Vivosoc] 2 core mixed-signal PULP system with a low-power A/D converter
* [http://asic.ethz.ch/2016/Vivosoc2.html Vivosoc2] 4 core mixed-signal PULP system with a low-power A/D converter (130nm)
+
* [http://asic.ethz.ch/2016/Vivosoc2.html Vivosoc2] 4 core mixed-signal PULP system with a low-power A/D converter, 128 kB L2,
* [http://asic.ethz.ch/2016/Vivosoc2.001.html Vivosoc2.001] updated version of 4 core mixed-signal PULP system with a low-power A/D converter (130nm)
+
* [http://asic.ethz.ch/2016/Vivosoc2.001.html Vivosoc2.001] updated version of 4 core mixed-signal PULP system with a low-power A/D converter
* [http://asic.ethz.ch/2016/Triphos.html Triphos] Power management IC for VivoSoC (130nm)
+
* [http://asic.ethz.ch/2018/Vivosoc3.html Vivosoc3] An even more updated version of 4 core mixed-signal PULP system with a low-power A/D converter
 +
* [http://asic.ethz.ch/2019/Vivosoc3.142.html Vivosoc3.142] Continued updates on the 4 core mixed-signal PULP system with a low-power A/D converter
 +
* [http://asic.ethz.ch/2016/Triphos.html Triphos] Power management IC for VivoSoC
  
 
====180nm====
 
====180nm====
Line 86: Line 72:
 
* [http://asic.ethz.ch/2015/Diego.html Diego] Large PULP chip with in-exact accelerators, LVT version  
 
* [http://asic.ethz.ch/2015/Diego.html Diego] Large PULP chip with in-exact accelerators, LVT version  
 
* [http://asic.ethz.ch/2015/Manny.html Manny] Large PULP chip with in-exact accelerators, sub-threshold version
 
* [http://asic.ethz.ch/2015/Manny.html Manny] Large PULP chip with in-exact accelerators, sub-threshold version
 
 
===Publications===
 
 
====2016====
 
 
* ''Accuracy and Performance Trade-offs of Logarithmic Number Units in Multi-Core Clusters'', M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, ARITH, 2016 (to appear)
 
 
* ''PULPino: A small single-core RISC-V SoC'', A. Traber, F. Zaruba, S. Stucki, A. Pullini, G. Haugou, E. Flamand, F. K. Gürkaynak, L. Benini, RISC-V Workshop, 2016, [http://riscv.org/workshop-jan2016/Wed1315%20PULP%20riscv3_noanim.pdf slides], [[Media:pulpino_poster_riscv2015.pdf|poster]]
 
 
* ''Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms'', F. Conti, D. Palossi, A. Marongiu, D. Rossi, L. Benini, DATE, 2016 (to appear)
 
 
* ''High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme'', Y. Popoff, F. Scheidegger, M. Schaffner, M. Gautschi, F. K. Gürkaynak, L. Benini, DATE, 2016 (to appear)
 
 
* ''A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster'', M. Gautschi, M. Schaffner, F. K. Gürkaynak, L. Benini, ISSCC, 2016, [http://dx.doi.org/10.1109/ISSCC.2016.7417917 paper]
 
 
====2015====
 
 
* ''A Ultra-Low-Energy Convolution Engine for Fast Brain-inspired Vision in Multicore Clusters'', F. Conti, L. Benini, DATE, 2015, [http://dl.acm.org/citation.cfm?id=2755753.2755910 paper]
 
 
* ''Lightweight virtual memory support for many-core accelerators in heterogeneous embedded SoCs'', P. Vogel, A. Marongiu, L. Benini, CODES+ISSS, 2015, [http://dx.doi.org/10.1109/CODESISSS.2015.7331367 paper]
 
 
* ''PULP: OpenRISC-based ultra-low power parallel platform'', D. Rossi, F. Conti, A. Pullini, I. Loi, M. Gautschi, D. Palossi, A. Marongiu, G. Haugou, L. Benini, ORCONF, 2015, [https://www.dropbox.com/s/qs3jbqqiz0948tj/PULP_ORCONF15.pptx?dl=0 slides][https://www.youtube.com/watch?v=HX-QHTMvuzk&list=PLUg3wIOWD8yoX2ECfeU_QP5snbu2Zs1Wp&index=3 video]
 
 
* ''PULPino: A RISC-V based single-core system'', A. Traber, S. Stucki, F. Zaruba, M. Gautschi, A. Pullini, I. Loi, D. Rossi, G. Haugou, F. K. Gürkaynak, L. Benini, ORCONF, 2015, [https://www.dropbox.com/s/vtrgqnc7dm7gbx2/Andreas%20Traber%20-%20pulpino.pdf?dl=0 slides][https://www.youtube.com/watch?v=-_zGoJmPddo&index=4&list=PLUg3wIOWD8yoX2ECfeU_QP5snbu2Zs1Wp video]
 
 
* ''Exploring Multi-banked Shared-L1 Program Cache on Ultra-Low Power Tightly Coupled Processor Clusters'', I. Loi, D. Rossi, G. Haugou, M. Gautschi, L. Benini, ACM Computing Frontiers, 2015, [http://dx.doi.org/10.1145/2742854.2747288 paper]
 
 
* ''PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, Journal of Signal Processing Systems, October 2015, [http://link.springer.com/article/10.1007%2Fs11265-015-1070-9 paper]
 
 
* ''A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, M. Gautschi, I. Loi, F.K. Gurkaynak, P. Flatresse, L. Benini, S3S, October 2015, [http://dx.doi.org/10.1109/S3S.2015.7333483 paper]
 
 
* ''A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology'', D. Rossi, A. Pullini, I. Loi, F. K. Gürkaynak, A. Bartolini, P. Flatresse, L. Benini, Solid-State Electronics, 2016, [http://dx.doi.org/10.1016/j.sse.2015.11.015 paper]
 
 
* ''PULP: A Parallel Ultra-Low-Power Platform for Next Generation IoT Applications'', D. Rossi, F. Conti, A. Marongiu, A. Pullini, I. Loi, M. Gautschi, G. Tagliavini, A. Capotondi, P. Flatresse, L. Benini, HOT Chips, 2015, [http://www.hotchips.org/wp-content/uploads/hc_archives/hc27/HC27.24-Monday-Epub/HC27.24.10-IoT-Epub/HC27.24.111-PULP-Rossi-DEL-ETH-2.pdf slides]
 
 
* ''Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores'', M. Gautschi, A. Traber, A. Pullini, L. Benini, M. Scandale, A. Di Federico, M. Beretta, G. Agosta, VLSI-SoC, 2015, [http://dx.doi.org/10.1109/VLSI-SoC.2015.7314386 paper]
 
 
 
====2014====
 
 
* ''Energy-efficient vision on the PULP platform for ultra-low power parallel computing'', F. Conti, D. Rossi, A. Pullini, I. Loi, L. Benini, SiPS, 2014, [http://dx.doi.org/10.1109/SiPS.2014.6986099 paper]
 
 
* ''Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters'', D. Rossi, I. Loi, G. Haugou, L. Benini, ACM Computing Frontiers, 2014, [http://dx.doi.org/10.1145/2597917.2597922 paper]
 
 
* ''Customizing an Open Source Processor to Fit in an Ultra-Low Power Cluster with a Shared L1 Memory'', M. Gautschi, D. Rossi, L. Benini, GLSVLSI, 2014, [http://dx.doi.org/10.1145/2591513.2591569 paper]
 
 
* ''Energy efficient parallel computing on the PULP platform with support for OpenMP'', D. Rossi, I. Loi, F. Conti, G. Tagliavini, A. Pullini, A. Marongiu, IEEEI, 2014, [http://dx.doi.org/10.1109/EEEI.2014.7005803 paper]
 
 
===Links===
 
* [http://www.pulp-platform.org Official PULP Project Website]
 
* [https://github.com/pulp-platform/pulpino PULPino on GitHub]
 
* [http://iis.ee.ethz.ch/~haugoug/pulp PULP SDK] (Software Development Kit)
 
* [http://www-micrel.deis.unibo.it/pulp-project PULP page in University of Bologna]
 
* [http://compilergroup.elet.polimi.it/doku.php?id=research:pulp LLVM compiler for PULP developed by Politecnico di Milano]
 
** [http://compilergroup-srv.elet.polimi.it/toolchains/or1k-toolchain-linux-amd64-latest.tar.gz Latest compiled toolchain for Linux EL6]
 
 
  
 
===Templates and Logos===
 
===Templates and Logos===
 
[[Media:pulp_logos.tar|This archive]] contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.
 
[[Media:pulp_logos.tar|This archive]] contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.
  
For documentation, please use the following [[Media:Pulp_ug_template_v1.0.tar.gz|Word template (v1.0)]]. And here is a PULP [[Media:Pulp_slide_template_v1.0.pptx|slide template for Powerpoint (v1.0)]].
+
For documentation, please use the following [[Media:Pulp_ug_template_v1.0.tar.gz|Word template (v1.0)]]. And here is a PULP [[Media:Pulp_slide_template_v1.1.pptx|slide template for Powerpoint (v1.1)]].
  
 
====Inline====
 
====Inline====

Latest revision as of 09:38, 11 September 2020

Layout of Pulp v3.


PULP logo (for different variants and file formats see below)


PULP - An Open Parallel Ultra-Low-Power Processing-Platform

Basic block diagram of a PULP system.

This is a joint project between the Integrated Systems Laboratory (IIS) of ETH Zurich and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.

The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.

See our Main Project webpage, our GitHub project page or follow us on Twitter for up to date information.

Related Available Student Projects


Related Chips

22nm

  • Poseidon A chip containing both PULPissimo (updated single core microcontroller with 32-bit core) and Ariane (64 bit RISC-V core)
  • Kosmodrom The chip contains two instances of an improved Ariane cores (with FPUs) optimized for different operation corners
  • Arnold Combines an eFPGA from Quicklogic and a 32bit PULPissimo system with a RI5CY with FPU support
  • Baikonur Two Ariane cores (similar to Kosmodrom) and introducing Bowtruckle a many core system around the Snitch core.
  • Thestral Snitch based system with 1x cluster (8x compute + 1x DMA core) and 1x governor core. Designed to test fine grained power gating solutions.

28nm

  • Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
  • Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
  • Pulp v3 The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
  • Honey Bunny PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.

40nm

  • Mr. Wolf new generation PULP system with 1 fabric controller (micro-riscy) and a cluster with eight RI5CY (RISC-V cores optimized for DSP operations) and two shared IEEE-754 FPUs.

65nm

  • Mia Wallace Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 kByte memory
  • Fulmine Third generation of PULP platform, Convolutional accelerator, crypto accelerator, body biasing FLLs, 256 kByte memory
  • Artemis 4 core PULP system including FPU.
  • Hecate 4 core PULP system with 2 shared FPUs.
  • Selene 4 core PULP system with 1 shared FPU using a logarithmic number system.
  • Diana 4 core PULP system with FPUs designed using approximate computing techniques.
  • Phoebe an improved version of Selene, 4 cores and 1 shared vectorial FPU using logarithmic number system
  • Imperio single core RISC-V based PULPino system. Has the PULP DNA, but is a single core microprocessor complete with peripherals from the PULP project.
  • Patronus chip with three separate single RISC-V cores. It is technically a newer PULPino (single core system)
  • Scarabaeus a 64-bit system with one Ariane core, peripherals, and a new interrupt controller.
  • Atomario multi-cluster system with two four-core RI5CY clusters.
  • Billywig multi-core system with a new Snitch core (RV32IMAFD) with extensions to improve stream processing
  • Plink Serial I/O interface for PULP
  • Urania BigPULP implementation with one Ariane core and two clusters each with 4x RI5CY cores and a DDR interface
  • Xavier PULPissimo system with multiple SPI ports, a uDMA with pre-processing capability and a QNE accelerator
  • Rosetta PULPissimo system with multiple in-memory computing accelerators.
  • Dustin PULP cluster with new SIMD extensions.

130nm

  • Vivosoc 2 core mixed-signal PULP system with a low-power A/D converter
  • Vivosoc2 4 core mixed-signal PULP system with a low-power A/D converter, 128 kB L2,
  • Vivosoc2.001 updated version of 4 core mixed-signal PULP system with a low-power A/D converter
  • Vivosoc3 An even more updated version of 4 core mixed-signal PULP system with a low-power A/D converter
  • Vivosoc3.142 Continued updates on the 4 core mixed-signal PULP system with a low-power A/D converter
  • Triphos Power management IC for VivoSoC

180nm

  • Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP.
  • Sir10us A cryptographic application that uses the Or10n processor developed for PULP.
  • Sid Large PULP chip with in-exact accelerators, LL version
  • Diego Large PULP chip with in-exact accelerators, LVT version
  • Manny Large PULP chip with in-exact accelerators, sub-threshold version

Templates and Logos

This archive contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.

For documentation, please use the following Word template (v1.0). And here is a PULP slide template for Powerpoint (v1.1).

Inline

Inline PULP logo, variant 2 (PNG PDF). Inline PULP logo, variant 1 (PNG PDF).

Big

Big PULP logo, variant 2 (PNG PDF). Big PULP logo, variant 1 (PNG PDF). Main PULP logo icon (PNG PDF).