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PULP

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Revision as of 15:19, 7 July 2015 by Kgf (talk | contribs) (PULP - an Open Parallel Ultra-Low-Power Processing-Platform)
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PULP - an Open Parallel Ultra-Low-Power Processing-Platform

This is a joint project between the Integrated Systems laboratory (IIS) of ETH Zurich (IIS) and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.

Inquiries from interested partners are welcome.

....more to follow.... stay tuned!

Related Available Projects

Related Chips

28nm

  • Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
  • Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
  • Pulp v3 The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.

65nm

  • Mia Wallace Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 Kbyte memory (65nm)
  • Artemis 4 core PULP system including FPU (65nm).
  • Hecate 4 core PULP system with 2 shared FPUs (65nm).
  • Selene 4 core PULP system with 1 shared FPU using a logarithmic number system (65nm).
  • Diana 4 core PULP system with FPUs designed using approximate computing techniques (65nm).

130nm

  • Vivosoc 2 core mixed-signal PULP system with a low-power A/D converter (130nm)

180nm

  • Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP (180nm).
  • Sir10us A cryptographic application that uses the Or10n processor developed for PULP (180nm).

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