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PULP

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PULP logo (for different variants and file formats see below)

PULP - an Open Parallel Ultra-Low-Power Processing-Platform

Basic block diagram of a PULP system

This is a joint project between the Integrated Systems laboratory (IIS) of ETH Zurich (IIS) and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open, scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.

The PULP platform is a multi-core platform achieving leading-edge energy-efficiency and featuring widely-tunable performance. The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, vital signs monitors. As opposed to single-core MCUs, a parallel ultra-low-power programmable architecture allows to meet the computational requirements of these applications, without exceeding the power envelope of a few mW typical of miniaturized, battery-powered systems. Moreover, OpenMP, OpenCL and OpenVX are supported on PULP, enabling agile application porting, development, performance tuning and debugging.

Inquiries from interested partners are welcome.

....more to follow.... stay tuned!

Related Available Projects

Related Chips

28nm

  • Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
  • Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
  • Pulp v3 The third version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator.
  • Honey Bunny PULp platform using RISC-V compliant RI5CY cores and Globalfoundries 28nm SLP technology. Four cores, 68 kBytes of TCDM and 256 kBytes of L2.

65nm

  • Mia Wallace Third generation of PULP platform, HW accelerators, body biasing FLLs, 256 Kbyte memory (65nm)
  • Artemis 4 core PULP system including FPU (65nm).
  • Hecate 4 core PULP system with 2 shared FPUs (65nm).
  • Selene 4 core PULP system with 1 shared FPU using a logarithmic number system (65nm).
  • Diana 4 core PULP system with FPUs designed using approximate computing techniques (65nm).

130nm

  • Vivosoc 2 core mixed-signal PULP system with a low-power A/D converter (130nm)

180nm

  • Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP.
  • Sir10us A cryptographic application that uses the Or10n processor developed for PULP.
  • Sid Large PULP chip with in-exact accelerators, LL version
  • Diego Large PULP chip with in-exact accelerators, LVT version
  • Manny Large PULP chip with in-exact accelerators, sub-threshold version

Links

Publications

For an up to date list of papers please see the Literature link of the PULP page in University of Bologna.

Logos

This archive contains all PULP logos below as well as inverted versions thereof for dark backgrounds (in PDF and PNG formats). Also, it includes the "Orbitron" font which has been used here.

Inline

Inline PULP logo, variant 2 (PNG PDF). Inline PULP logo, variant 1 (PNG PDF).

Small

Big PULP logo, variant 2 (PNG PDF). Big PULP logo, variant 1 (PNG PDF). Main PULP logo icon (PNG PDF).