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(Related Chips)
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* [http://asic.ethz.ch/2013/Or10n.html Or10n] An optimized implementation of the OpenRISC processor developed to be used within PULP.
 
* [http://asic.ethz.ch/2013/Or10n.html Or10n] An optimized implementation of the OpenRISC processor developed to be used within PULP.
 
* [http://asic.ethz.ch/2013/Sir10us.html Sir10us] A cryptographic application that uses the Or10n processor developed for PULP.
 
* [http://asic.ethz.ch/2013/Sir10us.html Sir10us] A cryptographic application that uses the Or10n processor developed for PULP.
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* [http://asic.ethz.ch/2014/Artemis.html Artemis] 4 core PULP system including FPU.
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* [http://asic.ethz.ch/2014/Hecate.html Artemis] 4 core PULP system with 2 shared FPUs.
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* [http://asic.ethz.ch/2014/Selene.html Artemis] 4 core PULP system with 1 shared FPU using a logarithmic number system.
  
 
===Links===
 
===Links===

Revision as of 14:47, 14 January 2015

PULP - an Open-Source Parallel Ultra-Low-Power Processing-Platform

This is a joint project between the Integrated Systems laboratory (IIS) of ETH Zurich (IIS) and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open-source scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.

Inquiries from interested partners are welcome.

....more to follow.... stay tuned!

Related Available Projects

Related Chips

  • Pulp v1 The first version of the PULP platform realized in 28nm FDSOI technology with 4 parallel cores.
  • Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP.
  • Sir10us A cryptographic application that uses the Or10n processor developed for PULP.
  • Artemis 4 core PULP system including FPU.
  • Artemis 4 core PULP system with 2 shared FPUs.
  • Artemis 4 core PULP system with 1 shared FPU using a logarithmic number system.

Links