Personal tools

Difference between revisions of "PULP"

From iis-projects

Jump to: navigation, search
(Links)
(Related Chips)
Line 16: Line 16:
 
* [http://asic.ethz.ch/2013/Pulp.html Pulp v1] The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.  
 
* [http://asic.ethz.ch/2013/Pulp.html Pulp v1] The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.  
 
* [http://asic.ethz.ch/2014/Pulpv2.html Pulp v2] The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.  
 
* [http://asic.ethz.ch/2014/Pulpv2.html Pulp v2] The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.  
* [http://asic.ethz.ch/2013/Or10n.html Or10n] An optimized implementation of the OpenRISC processor developed to be used within PULP.
+
* [http://asic.ethz.ch/2013/Or10n.html Or10n] An optimized implementation of the OpenRISC processor developed to be used within PULP (180nm).
* [http://asic.ethz.ch/2013/Sir10us.html Sir10us] A cryptographic application that uses the Or10n processor developed for PULP.
+
* [http://asic.ethz.ch/2013/Sir10us.html Sir10us] A cryptographic application that uses the Or10n processor developed for PULP (180nm).
* [http://asic.ethz.ch/2014/Artemis.html Artemis] 4 core PULP system including FPU.
+
* [http://asic.ethz.ch/2014/Artemis.html Artemis] 4 core PULP system including FPU (65nm).
* [http://asic.ethz.ch/2014/Hecate.html Hecate] 4 core PULP system with 2 shared FPUs.
+
* [http://asic.ethz.ch/2014/Hecate.html Hecate] 4 core PULP system with 2 shared FPUs (65nm).
* [http://asic.ethz.ch/2014/Selene.html Selene] 4 core PULP system with 1 shared FPU using a logarithmic number system.
+
* [http://asic.ethz.ch/2014/Selene.html Selene] 4 core PULP system with 1 shared FPU using a logarithmic number system (65nm).
* [http://asic.ethz.ch/2014/Diana.html Diana] 4 core PULP system with FPUs designed using approximate computing techniques
+
* [http://asic.ethz.ch/2014/Diana.html Diana] 4 core PULP system with FPUs designed using approximate computing techniques (65nm).
  
 
===Links===
 
===Links===

Revision as of 07:18, 24 January 2015

PULP - an Open-Source Parallel Ultra-Low-Power Processing-Platform

This is a joint project between the Integrated Systems laboratory (IIS) of ETH Zurich (IIS) and the Energy-efficient Embedded Systems (EEES) group of UNIBO to develop an open-source scalable Hardware and Software research platform with the goal to break the pJ/op barrier within a power envelope of a few mW.

Inquiries from interested partners are welcome.

....more to follow.... stay tuned!

Related Available Projects

Related Chips

  • Pulp v1 The first version of the PULP platform realized in 28nm FDSOI (RVT) technology with 4 parallel cores.
  • Pulp v2 The second version of the PULP platform realized in 28nm FDSOI (LVT) technology with 4 parallel cores.
  • Or10n An optimized implementation of the OpenRISC processor developed to be used within PULP (180nm).
  • Sir10us A cryptographic application that uses the Or10n processor developed for PULP (180nm).
  • Artemis 4 core PULP system including FPU (65nm).
  • Hecate 4 core PULP system with 2 shared FPUs (65nm).
  • Selene 4 core PULP system with 1 shared FPU using a logarithmic number system (65nm).
  • Diana 4 core PULP system with FPUs designed using approximate computing techniques (65nm).

Links