Difference between revisions of "Pirmin Vogel"
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Latest revision as of 14:39, 3 March 2020
Pirmin Vogel received his M.Sc. and Ph.D degree from the Swiss Federal Institute of Technology Zurich (ETHZ), Switzerland, in 2013 and 2018, respectively. During his Ph.D. his research focus was on digital signal processing and embedded heterogeneous systems on a chip with a focus on operating system, driver, runtime and programming model support for efficient and transparent accelerator programming.
In 2019, he joined lowRISC C.I.C., a Cambridge-based, not-for-profit company using collaborative engineering to develop and maintain open source silicon designs and tools, through a unique combination of skills, expertise and vision. Since Nov 2019, Pirmin is back in the Integrated Systems Laboratory where he is working for lowRISC.
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Projects in Progress
- Ibex: FPGA Optimizations
- Ibex: Bit-Manipulation Extension
- HERO: TLB Invalidation
- BigPULP: Shared Virtual Memory Multicluster Extensions
- BigPULP: Multicluster Synchronization Extensions
- Smart Virtual Memory Sharing
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
- Baseband Meets CPU
- Eﬃcient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems