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Showing below up to 250 results in range #251 to #500.

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  1. Sensor Fusion for Rockfall Sensor Node‏‎ (11:51, 21 August 2018)
  2. Development of a Rockfall Sensor Node‏‎ (11:55, 21 August 2018)
  3. BigPULP: Shared Virtual Memory Multicluster Extensions‏‎ (15:05, 23 August 2018)
  4. Cryptography‏‎ (21:04, 24 August 2018)
  5. IoT Turbo Decoder‏‎ (09:37, 14 September 2018)
  6. Shared Correlation Accelerator for an RF SoC‏‎ (09:38, 14 September 2018)
  7. Engineering For Kids‏‎ (16:11, 18 September 2018)
  8. Turbo Equalization for Cellular IoT‏‎ (11:43, 13 November 2018)
  9. PREM on PULP‏‎ (18:20, 20 November 2018)
  10. Taimir Aguacil‏‎ (16:24, 23 November 2018)
  11. Analog IC Design‏‎ (18:10, 4 December 2018)
  12. Brunn test‏‎ (12:02, 5 December 2018)
  13. Karim Badawi‏‎ (15:06, 5 December 2018)
  14. Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration‏‎ (15:50, 7 December 2018)
  15. Trace Debugger for custom RISC-V Core‏‎ (11:27, 11 December 2018)
  16. Digital Audio Interface for Smart Intensive Computing Triggering‏‎ (17:27, 22 January 2019)
  17. Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores‏‎ (21:21, 29 January 2019)
  18. Moritz Schneider‏‎ (16:36, 30 January 2019)
  19. Pulse Oximetry Fachpraktikum‏‎ (15:59, 18 February 2019)
  20. Elliptic Curve Accelerator for zkSNARKs‏‎ (15:02, 4 March 2019)
  21. Beat Cadence‏‎ (11:01, 18 March 2019)
  22. Deep Learning for Brain-Computer Interface‏‎ (20:22, 1 April 2019)
  23. Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path‏‎ (15:55, 6 May 2019)
  24. Ultra-low power sampling front-end for acquisition of physiological signals‏‎ (16:06, 6 May 2019)
  25. CMOS power amplifier for field measurements in MRI systems‏‎ (16:06, 6 May 2019)
  26. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications‏‎ (16:07, 6 May 2019)
  27. Design and implementation of the front-end for a portable ionizing radiation detector‏‎ (12:23, 9 May 2019)
  28. Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique‏‎ (10:30, 5 June 2019)
  29. Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation‏‎ (16:31, 5 June 2019)
  30. Freedom from Interference in Heterogeneous COTS SoCs‏‎ (17:40, 19 June 2019)
  31. Predictable Execution on GPU Caches‏‎ (17:41, 19 June 2019)
  32. PREM Intervals and Loop Tiling‏‎ (18:00, 19 June 2019)
  33. Compiler Profiling and Optimizing‏‎ (18:20, 19 June 2019)
  34. Extending the RISCV backend of LLVM to support PULP Extensions‏‎ (18:27, 19 June 2019)
  35. NAND Flash Open Research Platform‏‎ (11:06, 11 July 2019)
  36. Minimal Cost RISC-V core‏‎ (17:24, 21 August 2019)
  37. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks‏‎ (16:42, 27 August 2019)
  38. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM‏‎ (18:39, 3 September 2019)
  39. Influence of the Initial Filament Geometry on the Forming Step in CBRAM‏‎ (15:34, 4 September 2019)
  40. Simulation of Negative Capacitance Ferroelectric Transistor‏‎ (15:37, 4 September 2019)
  41. Computation of Phonon Bandstructure in III-V Nanostructures‏‎ (15:37, 4 September 2019)
  42. Design study of tunneling transistors based on a core/shell nanowire structures‏‎ (15:38, 4 September 2019)
  43. Investigation of the source starvation effect in III-V MOSFET‏‎ (15:40, 4 September 2019)
  44. Implementation of a 2-D model for Li-ion batteries‏‎ (15:41, 4 September 2019)
  45. Ab-initio Simulation of Strained Thermoelectric Materials‏‎ (15:43, 4 September 2019)
  46. Simulation of Li-ion batteries and comparison with experimental data‏‎ (15:43, 4 September 2019)
  47. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)‏‎ (15:44, 4 September 2019)
  48. Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea‏‎ (18:36, 5 September 2019)
  49. Design of Scalable Event-driven Neural-Recording Digital Interface‏‎ (18:40, 5 September 2019)
  50. Near-Memory Training of Neural Networks‏‎ (09:17, 11 September 2019)
  51. Application Specific Frequency Synthesizers (Analog/Digital PLLs)‏‎ (14:52, 25 September 2019)
  52. EECIS‏‎ (15:18, 25 September 2019)
  53. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea‏‎ (16:33, 3 October 2019)
  54. AnalogInt‏‎ (20:25, 25 October 2019)
  55. Cell Measurements for the 5G Internet of Things‏‎ (11:55, 29 October 2019)
  56. Herschmi‏‎ (15:03, 29 October 2019)
  57. Improving Resiliency of Hyperdimensional Computing‏‎ (15:51, 29 October 2019)
  58. Toward Superposition of Brain-Computer Interface Models‏‎ (15:52, 29 October 2019)
  59. Positioning for the cellular Internet of Things‏‎ (13:14, 31 October 2019)
  60. Interference Cancellation for the cellular Internet of Things‏‎ (13:15, 31 October 2019)
  61. Indoor Positioning with Bluetooth‏‎ (12:12, 4 November 2019)
  62. Design of an LTE Module for the Internet of Things‏‎ (14:20, 4 November 2019)
  63. Design of a VLIW processor architecture based on RISC-V‏‎ (10:25, 5 November 2019)
  64. Design of a Fused Multiply Add Floating Point Unit‏‎ (10:26, 5 November 2019)
  65. Audio Video Preprocessing In Parallel Ultra Low Power Platform‏‎ (10:27, 5 November 2019)
  66. PULPonFPGA: Hardware L2 Cache‏‎ (10:27, 5 November 2019)
  67. Image and Video Processing‏‎ (10:29, 5 November 2019)
  68. DMA Streaming Co-processor‏‎ (10:30, 5 November 2019)
  69. Developing a small portable neutron detector for detecting smuggled nuclear material‏‎ (10:32, 5 November 2019)
  70. Accelerators for object detection and tracking‏‎ (10:57, 5 November 2019)
  71. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors‏‎ (18:26, 5 November 2019)
  72. Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures‏‎ (18:33, 5 November 2019)
  73. Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications‏‎ (10:05, 18 November 2019)
  74. HERO: TLB Invalidation‏‎ (17:19, 18 November 2019)
  75. FPGA Testbed Implementation for Bluetooth Indoor Positioning‏‎ (21:47, 18 November 2019)
  76. PULPonFPGA: Lightweight Virtual Memory Support - Software Cache‏‎ (13:43, 29 November 2019)
  77. PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory‏‎ (13:43, 29 November 2019)
  78. Exploring Algorithms for Early Seizure Detection‏‎ (18:47, 6 January 2020)
  79. Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration‏‎ (20:12, 9 February 2020)
  80. Pirmin Vogel‏‎ (15:39, 3 March 2020)
  81. Real-Time ECG Contractions Classification‏‎ (19:15, 9 March 2020)
  82. Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex‏‎ (19:20, 9 March 2020)
  83. Final Presentation‏‎ (18:53, 22 March 2020)
  84. A computational memory unit using phase-change memory devices‏‎ (11:33, 17 April 2020)
  85. Accurate deep learning inference using computational memory‏‎ (12:51, 17 April 2020)
  86. Palm size chip NMR‏‎ (19:29, 7 May 2020)
  87. Timing Channel Mitigations for RISC-V Cores‏‎ (18:16, 20 May 2020)
  88. Nanoelectrode array biosensors - programmable non-overlapping clocks generator project‏‎ (07:56, 26 May 2020)
  89. Circuits and Systems for Nanoelectrode Array Biosensors‏‎ (13:27, 26 May 2020)
  90. An Energy Efficient Brain-Computer Interface using Mr.Wolf‏‎ (11:09, 21 July 2020)
  91. TCNs vs. LSTMs for Embedded Platforms‏‎ (11:10, 21 July 2020)
  92. Subject specific embeddings for transfer learning in brain-computer interfaces‏‎ (11:12, 21 July 2020)
  93. Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control‏‎ (11:22, 21 July 2020)
  94. A Snitch-based Compute Accelerator for HERO‏‎ (14:58, 29 July 2020)
  95. Tbenz‏‎ (16:48, 29 July 2020)
  96. Stefan Mach‏‎ (17:06, 29 July 2020)
  97. Floating-Point Divide & Square Root Unit for Transprecision‏‎ (17:09, 29 July 2020)
  98. IBM Research–Zurich‏‎ (17:40, 10 August 2020)
  99. Ibex: Bit-Manipulation Extension‏‎ (09:45, 28 August 2020)
  100. Ibex: FPGA Optimizations‏‎ (09:45, 28 August 2020)
  101. Deep Convolutional Autoencoder for iEEG Signals‏‎ (13:36, 9 September 2020)
  102. Positioning with Wireless Signals‏‎ (10:24, 28 September 2020)
  103. Heterogeneous SoCs‏‎ (18:41, 28 October 2020)
  104. Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs‏‎ (12:09, 29 October 2020)
  105. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development‏‎ (14:42, 29 October 2020)
  106. Channel Estimation for 5G Cellular IoT and Fast Fading Channels‏‎ (18:54, 29 October 2020)
  107. Power Optimization in Multipliers‏‎ (16:23, 30 October 2020)
  108. Evaluating the RiscV Architecture‏‎ (16:24, 30 October 2020)
  109. Energy Neutral Multi Sensors Wearable Device‏‎ (16:24, 30 October 2020)
  110. Bringing XNOR-nets (ConvNets) to Silicon‏‎ (16:25, 30 October 2020)
  111. Learning Image Compression with Convolutional Networks‏‎ (16:25, 30 October 2020)
  112. Improving our Smart Camera System‏‎ (16:26, 30 October 2020)
  113. AMZ Driverless Competition Embedded Systems Projects‏‎ (16:27, 30 October 2020)
  114. Nils Wistoff‏‎ (18:59, 30 October 2020)
  115. LightProbe‏‎ (14:14, 31 October 2020)
  116. IBM A2O Core‏‎ (11:15, 2 November 2020)
  117. PREM Runtime Scheduling Policies‏‎ (11:47, 2 November 2020)
  118. (M): A Flexible Peripheral System for High-Performance Systems on Chip‏‎ (12:16, 2 November 2020)
  119. Implementation of a Heterogeneous System for Image Processing on an FPGA‏‎ (12:48, 2 November 2020)
  120. SSR combined with FREP in LLVM/Clang‏‎ (13:02, 2 November 2020)
  121. DaCe on Snitch‏‎ (13:03, 2 November 2020)
  122. Implementation of a Heterogeneous System for Image Processing on an FPGA (S)‏‎ (17:26, 2 November 2020)
  123. MemPool on HERO‏‎ (18:42, 2 November 2020)
  124. ISA extensions in the Snitch Processor for Signal Processing (1M)‏‎ (19:24, 2 November 2020)
  125. Event-Driven Computing‏‎ (11:16, 5 November 2020)
  126. All-Digital In-Memory Processing‏‎ (12:23, 5 November 2020)
  127. A Recurrent Neural Network Speech Recognition Chip‏‎ (13:38, 10 November 2020)
  128. Energy-Efficient Brain-Inspired Hyperdimensional Computing‏‎ (13:38, 10 November 2020)
  129. Hardware Accelerators for Lossless Quantized Deep Neural Networks‏‎ (13:41, 10 November 2020)
  130. NVDLA meets PULP‏‎ (13:42, 10 November 2020)
  131. An Industrial-grade Bluetooth LE Mesh Network Solution‏‎ (15:34, 10 November 2020)
  132. Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices‏‎ (15:36, 10 November 2020)
  133. Embedded Gesture Recognition Using Novel Mini Radar Sensors‏‎ (15:36, 10 November 2020)
  134. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications‏‎ (15:37, 10 November 2020)
  135. Indoor Smart Tracking of Hospital instrumentation‏‎ (15:37, 10 November 2020)
  136. Wireless Sensing With Long Range Comminication (LoRa)‏‎ (15:37, 10 November 2020)
  137. Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing‏‎ (15:38, 10 November 2020)
  138. Edge Computing for Long-Term Wearable Biomedical Systems‏‎ (15:38, 10 November 2020)
  139. Efficient Search Design for Hyperdimensional Computing‏‎ (15:39, 10 November 2020)
  140. Improving Cold-Start in Batteryless And Energy Harvesting Systems‏‎ (15:41, 10 November 2020)
  141. Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration‏‎ (15:41, 10 November 2020)
  142. Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion‏‎ (15:41, 10 November 2020)
  143. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras‏‎ (15:41, 10 November 2020)
  144. Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX‏‎ (15:45, 10 November 2020)
  145. High-throughput Embedded System For Neurotechnology in collaboration with INI‏‎ (15:48, 10 November 2020)
  146. Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles‏‎ (15:48, 10 November 2020)
  147. Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring‏‎ (15:48, 10 November 2020)
  148. Embedded Systems and autonomous UAVs‏‎ (16:59, 10 November 2020)
  149. Predictable Execution‏‎ (18:48, 10 November 2020)
  150. IP-Based SoC Generation and Configuration (1-3S)‏‎ (20:24, 10 November 2020)
  151. Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers‏‎ (11:08, 12 November 2020)
  152. Low-Resolution 5G Beamforming Codebook Design‏‎ (11:37, 12 November 2020)
  153. Real-Time Optimization‏‎ (13:57, 12 November 2020)
  154. Deep Unfolding of Iterative Optimization Algorithms‏‎ (13:57, 12 November 2020)
  155. LightProbe - CNN-Based-Image-Reconstruction‏‎ (20:46, 12 November 2020)
  156. LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)‏‎ (20:47, 12 November 2020)
  157. Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)‏‎ (20:48, 12 November 2020)
  158. Ultrasound High Speed Microbubble Tracking‏‎ (20:49, 12 November 2020)
  159. LightProbe - Thermal-Power aware on-head Beamforming‏‎ (20:50, 12 November 2020)
  160. LightProbe - Frontend Firmware and Control Side Channel‏‎ (20:51, 12 November 2020)
  161. 3D Ultrasound Bubble Tracking‏‎ (20:52, 12 November 2020)
  162. Satellite Internet of Things‏‎ (13:53, 13 November 2020)
  163. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things‏‎ (13:54, 13 November 2020)
  164. Next Generation Channel Decoder‏‎ (14:01, 13 November 2020)
  165. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications‏‎ (15:31, 16 November 2020)
  166. FFT HDL Code Generator for Multi-Antenna mmWave Communication‏‎ (19:40, 16 November 2020)
  167. Autonomus Drones With Novel Sensors And Ultra Wide Band‏‎ (11:39, 30 November 2020)
  168. Smart Patch For Heath Care And Rehabilitation‏‎ (16:24, 30 November 2020)
  169. Matheus Cavalcante‏‎ (18:33, 8 December 2020)
  170. Improved Reacquisition for the 5G Cellular IoT‏‎ (14:04, 11 January 2021)
  171. ASIC Design of a Gaussian Message Passing Processor‏‎ (08:34, 20 January 2021)
  172. ASIC Design of a Sigma Point Processor‏‎ (08:34, 20 January 2021)
  173. Hardware Accelerator for Model Predictive Controller‏‎ (08:35, 20 January 2021)
  174. Fast Wakeup From Deep Sleep State‏‎ (08:35, 20 January 2021)
  175. Compressed Sensing for Wireless Biosignal Monitoring‏‎ (08:35, 20 January 2021)
  176. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP‏‎ (08:36, 20 January 2021)
  177. Autoencoder Accelerator for On-Chip Semi-Supervised Learning‏‎ (08:37, 20 January 2021)
  178. Extend the RI5CY core with priviledge extensions‏‎ (08:38, 20 January 2021)
  179. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core‏‎ (08:42, 20 January 2021)
  180. MemPool on HERO (1S)‏‎ (19:07, 20 January 2021)
  181. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core‏‎ (19:05, 29 January 2021)
  182. Resilient Brain-Inspired Hyperdimensional Computing Architectures‏‎ (19:08, 29 January 2021)
  183. Level Crossing ADC For a Many Channels Neural Recording Interface‏‎ (19:10, 29 January 2021)
  184. RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB‏‎ (19:10, 29 January 2021)
  185. Spiking Neural Network for Autonomous Navigation‏‎ (19:10, 29 January 2021)
  186. Event-Driven Convolutional Neural Network Modular Accelerator‏‎ (19:10, 29 January 2021)
  187. ASIC Design Projects‏‎ (19:13, 29 January 2021)
  188. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core‏‎ (19:19, 29 January 2021)
  189. A Snitch-based Compute Accelerator for HERO (M/1-2S)‏‎ (23:59, 6 February 2021)
  190. Heroino: Design of the next CORE-V Microcontroller‏‎ (00:01, 7 February 2021)
  191. VLSI Implementation of a 5G Ciphering Accelerator‏‎ (10:05, 9 February 2021)
  192. OTDOA Positioning for LTE Cat-M‏‎ (15:50, 9 February 2021)
  193. ASIC Development of 5G-NR LDPC Decoder‏‎ (01:43, 10 February 2021)
  194. Wireless Communication Systems for the IoT‏‎ (01:45, 10 February 2021)
  195. Software-Defined Paging in the Snitch Cluster (2-3S)‏‎ (20:08, 15 February 2021)
  196. Event-Driven Vision on an embedded platform‏‎ (08:41, 17 February 2021)
  197. Efficient TNN compression‏‎ (08:41, 17 February 2021)
  198. Design and Evaluation of a Small Size Avalanche Beacon‏‎ (10:02, 22 February 2021)
  199. ISA extensions in the Snitch Processor for Signal Processing (M)‏‎ (00:08, 13 March 2021)
  200. A Flexible Peripheral System for High-Performance Systems on Chip (M)‏‎ (15:40, 15 March 2021)
  201. Stand-Alone Edge Computing with GAP8‏‎ (14:38, 14 April 2021)
  202. Neural Networks Framwork for Embedded Plattforms‏‎ (14:40, 14 April 2021)
  203. Ibex: Tightly-Coupled Accelerators and ISA Extensions‏‎ (12:52, 27 April 2021)
  204. Intelligent Power Management Unit (iPMU)‏‎ (11:40, 2 June 2021)
  205. PULP in space - Fault Tolerant PULP System for Critical Space Applications‏‎ (14:46, 2 June 2021)
  206. Andreas Kurth‏‎ (07:40, 11 June 2021)
  207. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)‏‎ (12:21, 23 June 2021)
  208. Integrated silicon photonic structures-Lumiphase‏‎ (13:53, 23 June 2021)
  209. Integrated silicon photonic structures‏‎ (13:58, 23 June 2021)
  210. Phase-change memory devices for emerging computing paradigms‏‎ (14:13, 23 June 2021)
  211. Finite Element Simulations of Transistors for Quantum Computing‏‎ (14:14, 23 June 2021)
  212. Manycore System on FPGA (M/S/G)‏‎ (10:41, 6 July 2021)
  213. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)‏‎ (10:41, 6 July 2021)
  214. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)‏‎ (15:18, 9 July 2021)
  215. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)‏‎ (15:18, 9 July 2021)
  216. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)‏‎ (15:19, 9 July 2021)
  217. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)‏‎ (15:19, 9 July 2021)
  218. LLVM and DaCe for Snitch (1-2S)‏‎ (15:20, 9 July 2021)
  219. Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)‏‎ (15:21, 9 July 2021)
  220. Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)‏‎ (15:21, 9 July 2021)
  221. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (15:25, 9 July 2021)
  222. Unconventional phase change memory device concepts for in-memory and neuromorphic computin‏‎ (13:07, 23 July 2021)
  223. Test page‏‎ (12:30, 27 July 2021)
  224. Semi-Custom Digital VLSI for Processing-in-Memory‏‎ (14:33, 28 July 2021)
  225. SystemVerilog formatter for our LowRISC-based guidelines (2-3G)‏‎ (19:57, 29 July 2021)
  226. Fast Simulation of Manycore Systems (1S)‏‎ (17:20, 2 August 2021)
  227. Evaluating memory access pattern specializations in OoO, server-grade cores (M)‏‎ (13:25, 10 August 2021)
  228. DC-DC Buck converter in 65nm CMOS‏‎ (11:36, 20 August 2021)
  229. Low-Dropout Regulators for Magnetic Resonance Imaging‏‎ (11:38, 20 August 2021)
  230. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging‏‎ (11:40, 20 August 2021)
  231. Ultra-low power transceiver for implantable devices‏‎ (11:43, 20 August 2021)
  232. Inductive Charging Circuit for Implantable Devices‏‎ (11:43, 20 August 2021)
  233. Design of a 25 Gbps SerDes for optical chip-to-chip communication‏‎ (11:44, 20 August 2021)
  234. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT‏‎ (11:45, 20 August 2021)
  235. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT‏‎ (11:45, 20 August 2021)
  236. Design of Charge-Pump PLL in 22nm for 5G communication applications‏‎ (15:51, 20 August 2021)
  237. Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)‏‎ (10:54, 31 August 2021)
  238. Bluetooth Low Energy network with optimized data throughput‏‎ (17:18, 14 September 2021)
  239. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications‏‎ (15:31, 15 September 2021)
  240. 5G Cellular RF Front-end Design in 22nm CMOS Technology‏‎ (15:36, 15 September 2021)
  241. Analog building blocks for mmWave manipulation‏‎ (15:44, 15 September 2021)
  242. Low Latency Brain-Machine Interfaces‏‎ (09:18, 16 September 2021)
  243. Hyper-Dimensional Computing Based Predictive Maintenance‏‎ (09:18, 16 September 2021)
  244. Towards global Brain-Computer Interfaces‏‎ (09:20, 16 September 2021)
  245. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation‏‎ (09:23, 16 September 2021)
  246. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control‏‎ (09:25, 16 September 2021)
  247. Every individual on the planet should have a real chance to obtain personalized medical therapy‏‎ (17:04, 16 September 2021)
  248. Characterization techniques for silicon photonics-Lumiphase‏‎ (17:05, 16 September 2021)
  249. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials‏‎ (17:06, 16 September 2021)
  250. Electrothermal characterization of van der Waals Heterostructures with a partial overlap‏‎ (17:06, 16 September 2021)

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