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- Project Plan (13:41, 16 January 2014)
- Coding Guidelines (13:42, 16 January 2014)
- Project Meetings (13:47, 16 January 2014)
- Design Review (13:48, 16 January 2014)
- Assessment of novel photovoltaic architectures by circuit simulation (11:07, 17 January 2014)
- Processing of 3D Micro-tomography data for Lithium Ion Batteries (11:12, 17 January 2014)
- Developing High Efficiency Batteries for Electric Cars (11:28, 17 January 2014)
- Compressed Sensing Reconstruction on FPGA (17:56, 28 January 2014)
- High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS (16:28, 29 January 2014)
- Multi-Band Receiver Design for LTE Mobile Communication (16:47, 29 January 2014)
- High-Resolution, Calibrated Folding ADCs (17:02, 29 January 2014)
- Ultra-low power processor design (18:01, 30 January 2014)
- Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen (13:58, 8 March 2014)
- Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf (14:00, 8 March 2014)
- Reconfigurability of SHA-3 candidates (13:11, 13 March 2014)
- Variability Tolerant Ultra Low Power Cluster (09:52, 27 March 2014)
- Hardware Support for IDE in Multicore Environment (09:58, 27 March 2014)
- Christoph Keller (13:21, 27 March 2014)
- NORX - an AEAD algorithm for the CAESAR competition (10:13, 13 June 2014)
- Image Sensor Interface and Pre-processing (17:53, 6 December 2014)
- Atretter (10:20, 12 December 2014)
- Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip (17:06, 3 February 2015)
- A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance (09:43, 9 February 2015)
- Turbo Decoder Design for High Code Rates (09:45, 9 February 2015)
- High Throughput Turbo Decoder Design (09:46, 9 February 2015)
- IcySoC (11:48, 9 February 2015)
- Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA (12:49, 9 February 2015)
- Channel Decoding for TD-HSPA (12:55, 9 February 2015)
- Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon (12:56, 9 February 2015)
- Data Mapping for Unreliable Memories (12:56, 9 February 2015)
- Multiuser Equalization and Detection for 3GPP TD-SCDMA (13:07, 9 February 2015)
- Android reliability governor (16:24, 9 February 2015)
- Ultra Low Power Wake Up Radio for Wireless Sensor Network (18:54, 9 February 2015)
- Infrared Wake Up Radio (18:55, 9 February 2015)
- Ambient RF Energy harvesting for Wireless Sensor Network (18:56, 9 February 2015)
- Thermal Control of Mobile Devices (10:03, 10 February 2015)
- Successive Interference Cancellation for 3G Downlink (17:59, 10 February 2015)
- Channel Estimation for TD-HSPA (18:00, 10 February 2015)
- FPGA (18:50, 10 February 2015)
- ASIC (18:52, 10 February 2015)
- Design and Implementation of ultra low power vision system (15:46, 11 February 2015)
- Audio (16:28, 11 February 2015)
- Quantum Key Secured 100 Gbit/s Payload Encryption and its High-Speed Network Interfaces (19:06, 17 February 2015)
- Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator (19:06, 17 February 2015)
- Audio DAC Conversion Jitter Measurement System (19:06, 17 February 2015)
- Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems (19:10, 17 February 2015)
- Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC (09:04, 18 February 2015)
- Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC (09:06, 18 February 2015)
- Norbert Felber (12:56, 18 February 2015)
- Philipp Schönle (09:52, 10 March 2015)
- Flexible Front-End Circuit for Biomedical Data Acquisition (09:53, 10 March 2015)
- Wireless Biomedical Signal Acquisition Device (09:54, 10 March 2015)
- Benjamin Sporrer (12:01, 10 March 2015)
- High Performance Cellular Receivers in Very Advanced CMOS (12:02, 10 March 2015)
- Telecommunications (16:42, 24 March 2015)
- Design and Implementation of a Convolutional Neural Network Accelerator ASIC (18:45, 24 March 2015)
- Putting Together What Fits Together - GrÆStl (11:01, 26 March 2015)
- SHAre - An application Specific Instruction Set Processor for SHA-2/3 (11:09, 26 March 2015)
- High-Throughput Authenticated Encryption Architectures based on Block Ciphers (11:25, 26 March 2015)
- A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography (11:26, 26 March 2015)
- A Trustworthy Three-Factor Authentication System (13:01, 26 March 2015)
- A Multiview Synthesis Core in 65 nm CMOS (14:49, 13 May 2015)
- Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment (14:57, 13 May 2015)
- Real-time View Synthesis using Image Domain Warping (15:04, 13 May 2015)
- Evolved EDGE Physical Layer Incremental Redundancy Architecture (13:12, 27 May 2015)
- MatPHY: An Open-Source Physical Layer Development Framework (13:14, 27 May 2015)
- Autonomous Smart Watches: Hardware and Software Desing (10:59, 28 July 2015)
- A Wearable System for long term monitoring of human physiological parameters with E skin sensors (10:59, 28 July 2015)
- Eye movements (13:43, 29 July 2015)
- RazorEDGE: An Evolved EDGE DBB ASIC (16:15, 1 September 2015)
- Hardware/software co-programming on the Parallella platform (13:26, 2 September 2015)
- Real-Time Stereo to Multiview Conversion (08:09, 23 October 2015)
- Active-Set QP Solver on FPGA (12:09, 2 November 2015)
- Vector Processor for In-Memory Computing (12:10, 2 November 2015)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (15:42, 9 December 2015)
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC (16:07, 17 December 2015)
- EvalEDGE: A 2G Cellular Transceiver FMC (16:10, 17 December 2015)
- Design of a Digital Audio Module for Ultra-Low Power Cellular Applications (17:15, 17 December 2015)
- A Wireless Sensor Network for a Smart LED Lighting control (11:02, 27 January 2016)
- Bateryless Heart Rate Monitoring (14:21, 28 January 2016)
- Real-Time Optical Flow Using Neural Networks (10:22, 5 February 2016)
- Scattering Networks for Scene Labeling (10:29, 5 February 2016)
- Improving Scene Labeling with Hyperspectral Data (10:29, 5 February 2016)
- FFT-based Convolutional Network Accelerator (10:30, 5 February 2016)
- Real-Time Pedestrian Detection For Privacy Enhancement (12:17, 5 February 2016)
- Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification (11:11, 16 February 2016)
- Low-power Clock Generation Solutions for 65nm Technology (18:37, 3 March 2016)
- Final Report (09:22, 10 March 2016)
- NextGenChannelDec (14:31, 13 April 2016)
- ASIC Implementation of High-Throughput Next Generation Turbo Decoders (10:12, 14 April 2016)
- Channel Estimation and Equalization for LTE Advanced (10:13, 14 April 2016)
- Time Synchronization for 3G Mobile Communications (10:22, 14 April 2016)
- Signal to Noise Ratio Estimation for 3G standards (10:23, 14 April 2016)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (12:13, 14 April 2016)
- GSM Voice Capacity Evolution - VAMOS (16:45, 14 April 2016)
- 4th Generation Synchronization (16:56, 14 April 2016)
- Baseband Processor Development for 4G IoT (16:58, 14 April 2016)
- Beat DigRF (16:58, 14 April 2016)
- Research (18:38, 14 April 2016)
- Spatio-Temporal Video Filtering (18:40, 14 April 2016)
- 3D Turbo Decoder ASIC Realization (11:33, 15 April 2016)
- Implementing Hibernation on the ARM Cortex M0 (10:59, 20 June 2016)
- Digital Transmitter for Cellular IoT (15:41, 17 July 2016)
- An FPGA-Based Evaluation Platform for Mobile Communications (15:05, 21 July 2016)
- Non-binary LDPC Decoder for Deep-Space Optical Communications (15:05, 21 July 2016)
- Software (12:45, 8 August 2016)
- Towards Self Sustainable UAVs (19:45, 9 August 2016)
- Ultra Low Power Conversion Circuit For Batteryless Applications (16:46, 10 August 2016)
- Libria (08:35, 26 August 2016)
- Change-based Evaluation of Convolutional Neural Networks (17:04, 29 August 2016)
- Learning Image Decompression with Convolutional Networks (17:16, 29 August 2016)
- FPGA System Design for Computer Vision with Convolutional Neural Networks (17:17, 29 August 2016)
- High-speed Scene Labeling on FPGA (17:18, 29 August 2016)
- David J. Mack (16:41, 31 August 2016)
- Eye tracking (16:43, 31 August 2016)
- Linux Driver for fine-grain and low overhead access to on-chip performance counters (14:55, 9 September 2016)
- Open Power-On Chip Controller Study and Integration (14:57, 9 September 2016)
- PVT Dynamic Adaptation in PULPv3 (14:31, 13 September 2016)
- Compressed Sensing vs JPEG (09:24, 14 September 2016)
- On-chip clock synthesizer design and porting (10:20, 14 September 2016)
- FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications (10:15, 23 September 2016)
- Physical Layer Implementation of HSPA+ 4G Mobile Transceiver (10:16, 23 September 2016)
- Synchronization and Power Control Concepts for 3GPP TD-SCDMA (10:17, 23 September 2016)
- Channel Estimation for 3GPP TD-SCDMA (10:17, 23 September 2016)
- Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors (13:50, 30 November 2016)
- Ultra-Efficient Visual Classification on Movidius Myriad2 (13:57, 30 November 2016)
- Rethinking our Convolutional Network Accelerator Architecture (17:52, 12 December 2016)
- Ultra Low-Power Oscillator (17:58, 19 December 2016)
- OpenRISC SoC for Sensor Applications (14:23, 23 December 2016)
- Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication (15:13, 29 December 2016)
- LightProbe - Design of a High-Speed Optical Link (09:55, 10 January 2017)
- LightProbe - Ultracompact Power Supply PCB (09:56, 10 January 2017)
- DigitalUltrasoundHead (10:52, 10 January 2017)
- Single-Bit-Synapse Spiking Neural System-on-Chip (11:22, 13 January 2017)
- Tiny CNNs for Ultra-Efficient Object Detection on PULP (12:19, 13 January 2017)
- Gomeza old project3 (17:04, 28 January 2017)
- Gomeza old project2 (17:04, 28 January 2017)
- Gomeza old project1 (17:04, 28 January 2017)
- Gomeza old project5 (17:25, 28 January 2017)
- Gomeza old project4 (18:08, 28 January 2017)
- Development of a syringe label reader for the neurocritical care unit (12:00, 22 February 2017)
- Open Source Baseband Firmware for 2G Cellular Networks (10:30, 24 February 2017)
- Power Saver Mode for Cellular Internet of Things Receivers (16:59, 29 March 2017)
- Make Cellular Internet of Things Receivers Smart (17:00, 29 March 2017)
- Build the Fastest 2G Modem Ever (17:00, 29 March 2017)
- Digital Audio Processor for Cellular Applications (17:01, 29 March 2017)
- High performance continous-time Delta-Sigma ADC for biomedical applications (16:46, 2 May 2017)
- Deconvolution Accelerator for On-Chip Semi-Supervised Learning (13:48, 30 May 2017)
- Towards Online Training of CNNs: Hebbian-Based Deep Learning (18:50, 30 May 2017)
- Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams (18:52, 30 May 2017)
- LAPACK/BLAS for FPGA (11:38, 1 June 2017)
- Efficient Implementation of an Active-Set QP Solver for FPGAs (11:39, 1 June 2017)
- Accelerator for Spatio-Temporal Video Filtering (11:40, 1 June 2017)
- Variable Bit Precision Logic for Deep Learning and Artificial Intelligence (09:43, 26 June 2017)
- Kinetic Energy Harvesting For Autonomous Smart Watches (10:06, 12 July 2017)
- Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy (10:38, 21 July 2017)
- Radio Signal Direction Detection For Smart Glasses For Augmented Reality Applications (10:38, 21 July 2017)
- Towards The Integration of E-skin into Prosthetic Devices (10:39, 21 July 2017)
- Using Motion Sensors to Support Indoor Localization (10:41, 21 July 2017)
- Design of State Retentive Flip-Flops (08:34, 25 July 2017)
- Passive and Self Sustaining Receivers For On and Intra Body Communication For Wearable Sensors Networks (15:58, 28 July 2017)
- Low Power Neural Network For Multi Sensors Wearable Devices (16:02, 28 July 2017)
- Neural Processing (14:41, 7 August 2017)
- Accelerator for Boosted Binary Features (10:51, 19 August 2017)
- FPGA acceleration of ultrasound computed tomography for in vivo tumor screening (13:07, 30 August 2017)
- Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device (15:15, 1 September 2017)
- Glitches Reduce Listening Time of Your iPod (14:59, 14 September 2017)
- Internet of Things Network Synchronizer (19:00, 26 September 2017)
- Digital Transmitter for Mobile Communications (19:00, 26 September 2017)
- FPGA-Based Digital Frontend for 3G Receivers (19:01, 26 September 2017)
- Baseband Meets CPU (19:02, 26 September 2017)
- Hardware Accelerated Derivative Pricing (08:42, 12 October 2017)
- Hardware Accelerator Integration into Embedded Linux (08:46, 12 October 2017)
- Sandro Belfanti (16:27, 1 November 2017)
- Harald Kröll (16:27, 1 November 2017)
- Internet of Things SoC Characterization (09:37, 6 November 2017)
- VLSI Implementation of a Low-Complexity Channel Shortener for 2G EC-GSM-IoT and Evolved EDGE (09:39, 6 November 2017)
- WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing (09:39, 6 November 2017)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (09:39, 6 November 2017)
- Synchronisation and Cyclic Prefix Handling For LTE Testbed (09:40, 6 November 2017)
- Reading The GSM Beacon Carrier with OsmocomBB and stoneEDGE (09:40, 6 November 2017)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (09:43, 6 November 2017)
- Time and Frequency Synchronization in LTE Cat-0 Devices (09:43, 6 November 2017)
- Sub Noise Floor Channel Estimation for the Cellular Internet of Things (10:27, 6 November 2017)
- Low-power chip-to-chip communication network (11:34, 7 November 2017)
- Frank K. Gürkaynak (11:36, 7 November 2017)
- Michael Muehlberghuber (11:39, 7 November 2017)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (16:57, 7 November 2017)
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB (16:57, 7 November 2017)
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions (16:57, 7 November 2017)
- Hyper Meccano: Acceleration of Hyperdimensional Computing (12:58, 9 November 2017)
- Digital Beamforming for Ultrasound Imaging (10:23, 10 November 2017)
- CPS Software-Configurable State-Machine (10:24, 10 November 2017)
- State-Saving @ NXP (10:34, 10 November 2017)
- Pascal Hager (10:40, 10 November 2017)
- Low Power Embedded Systems (16:28, 13 November 2017)
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC (12:53, 14 November 2017)
- Smart Virtual Memory Sharing (11:16, 17 November 2017)
- Real-Time Implementation of Quantum State Identification using an FPGA (08:03, 21 December 2017)
- Design of low-offset dynamic comparators (16:35, 21 December 2017)
- Receiver design for the DigRF 4G high speed serial link (16:37, 21 December 2017)
- LTE-Advanced RF Front-end Design in 28nm CMOS Technology (16:38, 21 December 2017)
- Successive Approximation Register (SAR) ADC (16:43, 21 December 2017)
- Analog Layout Engine (16:44, 21 December 2017)
- Mattia (17:47, 21 December 2017)
- Low Power Geolocalization And Indoor Localization (12:36, 11 January 2018)
- BigPULP: Multicluster Synchronization Extensions (11:17, 22 January 2018)
- High Speed FPGA Trigger Logic for Particle Physics Experiments (20:42, 30 January 2018)
- Autonomous Sensors For Underwater Monitoring In Smart Navy Systems (16:21, 31 January 2018)
- Smart Wearable System For Vital Sign Monitoring Exploiting On Board and Cloud Machine Learning (16:21, 31 January 2018)
- A Wearable System To Control Phone And Electronic Device Without Hands (16:22, 31 January 2018)
- Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor (10:40, 2 February 2018)
- Wake Up Radio For Energy Efficient Communication System and IC Design (10:54, 2 February 2018)
- Zero Power Touch Sensor and Reciever For Body Communication (10:58, 2 February 2018)
- Monocular Vision-based Object Following on Nano-size Robotic Blimp (15:14, 20 February 2018)
- Covariant Feature Detector on Parallel Ultra Low Power Architecture (15:16, 20 February 2018)
- Towards Self-Sustainable Unmanned Aerial Vehicles (15:17, 20 February 2018)
- Study and Development of Intelligent Capability for Small-Size UAVs (15:18, 20 February 2018)
- Towards Autonomous Navigation for Nano-Blimps (15:20, 20 February 2018)
- Self-Learning Drones based on Neural Networks (15:26, 20 February 2018)
- A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments (15:35, 20 February 2018)
- Design and Implementation of an Approximate Floating Point Unit (09:58, 21 February 2018)
- Fabian Schuiki (10:02, 21 February 2018)
- Biomedical Systems on Chip (18:55, 22 February 2018)
- PULP-Shield for Autonomous UAV (10:06, 23 February 2018)
- Signal-Processing and Data-Compression on Beaglebone Black used as embedded HPC-performance-monitoring device (15:19, 27 February 2018)
- Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device (15:19, 27 February 2018)
- A Wireless Sensor Network for HPC monitoring (15:22, 27 February 2018)
- Interference Cancellation for EC-GSM-IoT (18:52, 21 March 2018)
- Hyperdimensional Computing (09:46, 25 April 2018)
- Charging System for Implantable Electronics (12:05, 27 April 2018)
- GUI-developement for an action-cam-based eye tracking device (10:10, 3 May 2018)
- Switched Capacitor Based Bandgap-Reference (10:13, 3 May 2018)
- Efficient NB-IoT Uplink Design (15:58, 7 May 2018)
- LTE IoT Network Synchronization (15:32, 18 May 2018)
- Sub-Noise Floor Channel Tracking (15:33, 18 May 2018)
- Enabling Standalone Operation (13:41, 23 May 2018)
- Optimal System Duty Cycling (13:44, 23 May 2018)
- Standard Cell Compatible Memory Array Design (14:54, 23 May 2018)
- Implementation of a NB-IoT Positioning System (15:36, 23 May 2018)
- Embedded Artificial Intelligence:Systems And Applications (12:52, 12 June 2018)
- Physics is looking for PULP (15:50, 21 June 2018)
- Creating a HDMI Video Interface for PULP (08:37, 10 July 2018)
- A Wireless Sensor Network for a Smart Building Monitor and Control (20:42, 30 July 2018)
- Ultrafast Medical Ultrasound imaging on a GPU (11:13, 1 August 2018)
- Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node (09:14, 3 August 2018)
- Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets (09:55, 3 August 2018)
- Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets (10:50, 3 August 2018)
- Fast and Accurate Multiclass Inference for Brain–Computer Interfaces (16:53, 7 August 2018)
- FPGA Optimizations of Dense Binary Hyperdimensional Computing (09:11, 8 August 2018)
- Sensor Fusion for Rockfall Sensor Node (10:51, 21 August 2018)
- Development of a Rockfall Sensor Node (10:55, 21 August 2018)
- BigPULP: Shared Virtual Memory Multicluster Extensions (14:05, 23 August 2018)
- Cryptography (20:04, 24 August 2018)
- IoT Turbo Decoder (08:37, 14 September 2018)
- Shared Correlation Accelerator for an RF SoC (08:38, 14 September 2018)
- Engineering For Kids (15:11, 18 September 2018)
- Turbo Equalization for Cellular IoT (10:43, 13 November 2018)
- PREM on PULP (17:20, 20 November 2018)
- Taimir Aguacil (15:24, 23 November 2018)
- Analog IC Design (17:10, 4 December 2018)
- Brunn test (11:02, 5 December 2018)
- Karim Badawi (14:06, 5 December 2018)
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration (14:50, 7 December 2018)
- Trace Debugger for custom RISC-V Core (10:27, 11 December 2018)
- Digital Audio Interface for Smart Intensive Computing Triggering (16:27, 22 January 2019)
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores (20:21, 29 January 2019)
- Moritz Schneider (15:36, 30 January 2019)
- Pulse Oximetry Fachpraktikum (14:59, 18 February 2019)
- Elliptic Curve Accelerator for zkSNARKs (14:02, 4 March 2019)
- Beat Cadence (10:01, 18 March 2019)
- Deep Learning for Brain-Computer Interface (19:22, 1 April 2019)
- Switched-capacitor power amplifier for IoT mobile communications: design of signal processing path (14:55, 6 May 2019)
- Ultra-low power sampling front-end for acquisition of physiological signals (15:06, 6 May 2019)
- CMOS power amplifier for field measurements in MRI systems (15:06, 6 May 2019)
- Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications (15:07, 6 May 2019)
- Design and implementation of the front-end for a portable ionizing radiation detector (11:23, 9 May 2019)
- Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique (09:30, 5 June 2019)
- Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation (15:31, 5 June 2019)
- Freedom from Interference in Heterogeneous COTS SoCs (16:40, 19 June 2019)
- Predictable Execution on GPU Caches (16:41, 19 June 2019)
- PREM Intervals and Loop Tiling (17:00, 19 June 2019)
- Compiler Profiling and Optimizing (17:20, 19 June 2019)
- Extending the RISCV backend of LLVM to support PULP Extensions (17:27, 19 June 2019)
- NAND Flash Open Research Platform (10:06, 11 July 2019)
- Minimal Cost RISC-V core (16:24, 21 August 2019)
- A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks (15:42, 27 August 2019)
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM (17:39, 3 September 2019)
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM (14:34, 4 September 2019)
- Simulation of Negative Capacitance Ferroelectric Transistor (14:37, 4 September 2019)
- Computation of Phonon Bandstructure in III-V Nanostructures (14:37, 4 September 2019)
- Design study of tunneling transistors based on a core/shell nanowire structures (14:38, 4 September 2019)
- Investigation of the source starvation effect in III-V MOSFET (14:40, 4 September 2019)
- Implementation of a 2-D model for Li-ion batteries (14:41, 4 September 2019)
- Ab-initio Simulation of Strained Thermoelectric Materials (14:43, 4 September 2019)
- Simulation of Li-ion batteries and comparison with experimental data (14:43, 4 September 2019)
- Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs) (14:44, 4 September 2019)
- Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea (17:36, 5 September 2019)
- Design of Scalable Event-driven Neural-Recording Digital Interface (17:40, 5 September 2019)
- Near-Memory Training of Neural Networks (08:17, 11 September 2019)
- Application Specific Frequency Synthesizers (Analog/Digital PLLs) (13:52, 25 September 2019)
- EECIS (14:18, 25 September 2019)
- Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea (15:33, 3 October 2019)
- AnalogInt (19:25, 25 October 2019)
- Cell Measurements for the 5G Internet of Things (10:55, 29 October 2019)
- Herschmi (14:03, 29 October 2019)
- Improving Resiliency of Hyperdimensional Computing (14:51, 29 October 2019)
- Toward Superposition of Brain-Computer Interface Models (14:52, 29 October 2019)
- Positioning for the cellular Internet of Things (12:14, 31 October 2019)
- Interference Cancellation for the cellular Internet of Things (12:15, 31 October 2019)
- Indoor Positioning with Bluetooth (11:12, 4 November 2019)
- Design of an LTE Module for the Internet of Things (13:20, 4 November 2019)
- Design of a VLIW processor architecture based on RISC-V (09:25, 5 November 2019)
- Design of a Fused Multiply Add Floating Point Unit (09:26, 5 November 2019)
- Audio Video Preprocessing In Parallel Ultra Low Power Platform (09:27, 5 November 2019)
- PULPonFPGA: Hardware L2 Cache (09:27, 5 November 2019)
- Image and Video Processing (09:29, 5 November 2019)
- DMA Streaming Co-processor (09:30, 5 November 2019)
- Developing a small portable neutron detector for detecting smuggled nuclear material (09:32, 5 November 2019)
- Accelerators for object detection and tracking (09:57, 5 November 2019)
- Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors (17:26, 5 November 2019)
- Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures (17:33, 5 November 2019)
- Ternary Weights Engine For Efficient Many Channels Spike Sorting Applications (09:05, 18 November 2019)
- HERO: TLB Invalidation (16:19, 18 November 2019)
- FPGA Testbed Implementation for Bluetooth Indoor Positioning (20:47, 18 November 2019)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (12:43, 29 November 2019)
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory (12:43, 29 November 2019)
- Exploring Algorithms for Early Seizure Detection (17:47, 6 January 2020)
- Toward hyperdimensional active perception: learning compressed sensorimotor control by demonstration (19:12, 9 February 2020)
- Pirmin Vogel (14:39, 3 March 2020)
- Real-Time ECG Contractions Classification (18:15, 9 March 2020)
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex (18:20, 9 March 2020)
- Final Presentation (17:53, 22 March 2020)
- A computational memory unit using phase-change memory devices (10:33, 17 April 2020)
- Accurate deep learning inference using computational memory (11:51, 17 April 2020)
- Palm size chip NMR (18:29, 7 May 2020)
- Timing Channel Mitigations for RISC-V Cores (17:16, 20 May 2020)
- Nanoelectrode array biosensors - programmable non-overlapping clocks generator project (06:56, 26 May 2020)
- Circuits and Systems for Nanoelectrode Array Biosensors (12:27, 26 May 2020)
- An Energy Efficient Brain-Computer Interface using Mr.Wolf (10:09, 21 July 2020)
- TCNs vs. LSTMs for Embedded Platforms (10:10, 21 July 2020)
- Subject specific embeddings for transfer learning in brain-computer interfaces (10:12, 21 July 2020)
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control (10:22, 21 July 2020)
- A Snitch-based Compute Accelerator for HERO (13:58, 29 July 2020)
- Tbenz (15:48, 29 July 2020)
- Stefan Mach (16:06, 29 July 2020)
- Floating-Point Divide & Square Root Unit for Transprecision (16:09, 29 July 2020)
- IBM Research–Zurich (16:40, 10 August 2020)
- Ibex: Bit-Manipulation Extension (08:45, 28 August 2020)
- Ibex: FPGA Optimizations (08:45, 28 August 2020)
- Deep Convolutional Autoencoder for iEEG Signals (12:36, 9 September 2020)
- Positioning with Wireless Signals (09:24, 28 September 2020)
- Heterogeneous SoCs (17:41, 28 October 2020)
- Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs (11:09, 29 October 2020)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development (13:42, 29 October 2020)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels (17:54, 29 October 2020)
- Power Optimization in Multipliers (15:23, 30 October 2020)
- Evaluating the RiscV Architecture (15:24, 30 October 2020)
- Energy Neutral Multi Sensors Wearable Device (15:24, 30 October 2020)
- Bringing XNOR-nets (ConvNets) to Silicon (15:25, 30 October 2020)
- Learning Image Compression with Convolutional Networks (15:25, 30 October 2020)
- Improving our Smart Camera System (15:26, 30 October 2020)
- AMZ Driverless Competition Embedded Systems Projects (15:27, 30 October 2020)
- Nils Wistoff (17:59, 30 October 2020)
- LightProbe (13:14, 31 October 2020)
- IBM A2O Core (10:15, 2 November 2020)
- PREM Runtime Scheduling Policies (10:47, 2 November 2020)
- (M): A Flexible Peripheral System for High-Performance Systems on Chip (11:16, 2 November 2020)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (11:48, 2 November 2020)
- SSR combined with FREP in LLVM/Clang (12:02, 2 November 2020)
- DaCe on Snitch (12:03, 2 November 2020)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (16:26, 2 November 2020)
- MemPool on HERO (17:42, 2 November 2020)
- ISA extensions in the Snitch Processor for Signal Processing (1M) (18:24, 2 November 2020)
- Event-Driven Computing (10:16, 5 November 2020)
- All-Digital In-Memory Processing (11:23, 5 November 2020)
- A Recurrent Neural Network Speech Recognition Chip (12:38, 10 November 2020)
- Energy-Efficient Brain-Inspired Hyperdimensional Computing (12:38, 10 November 2020)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (12:41, 10 November 2020)
- NVDLA meets PULP (12:42, 10 November 2020)
- An Industrial-grade Bluetooth LE Mesh Network Solution (14:34, 10 November 2020)
- Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices (14:36, 10 November 2020)
- Embedded Gesture Recognition Using Novel Mini Radar Sensors (14:36, 10 November 2020)
- A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications (14:37, 10 November 2020)
- Indoor Smart Tracking of Hospital instrumentation (14:37, 10 November 2020)
- Wireless Sensing With Long Range Comminication (LoRa) (14:37, 10 November 2020)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (14:38, 10 November 2020)
- Edge Computing for Long-Term Wearable Biomedical Systems (14:38, 10 November 2020)
- Efficient Search Design for Hyperdimensional Computing (14:39, 10 November 2020)
- Improving Cold-Start in Batteryless And Energy Harvesting Systems (14:41, 10 November 2020)
- Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration (14:41, 10 November 2020)
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion (14:41, 10 November 2020)
- Adversarial Attacks Against Deep Neural Networks In Wearable Cameras (14:41, 10 November 2020)
- Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX (14:45, 10 November 2020)
- High-throughput Embedded System For Neurotechnology in collaboration with INI (14:48, 10 November 2020)
- Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles (14:48, 10 November 2020)
- Pressure and acoustic Smart Sensors Network for Wind Turbines Monitoring (14:48, 10 November 2020)
- Embedded Systems and autonomous UAVs (15:59, 10 November 2020)
- Predictable Execution (17:48, 10 November 2020)
- IP-Based SoC Generation and Configuration (1-3S) (19:24, 10 November 2020)
- Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers (10:08, 12 November 2020)
- Low-Resolution 5G Beamforming Codebook Design (10:37, 12 November 2020)
- Real-Time Optimization (12:57, 12 November 2020)
- Deep Unfolding of Iterative Optimization Algorithms (12:57, 12 November 2020)
- LightProbe - CNN-Based-Image-Reconstruction (19:46, 12 November 2020)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (19:47, 12 November 2020)
- Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) (19:48, 12 November 2020)
- Ultrasound High Speed Microbubble Tracking (19:49, 12 November 2020)
- LightProbe - Thermal-Power aware on-head Beamforming (19:50, 12 November 2020)
- LightProbe - Frontend Firmware and Control Side Channel (19:51, 12 November 2020)
- 3D Ultrasound Bubble Tracking (19:52, 12 November 2020)
- Satellite Internet of Things (12:53, 13 November 2020)
- FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things (12:54, 13 November 2020)
- Next Generation Channel Decoder (13:01, 13 November 2020)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (14:31, 16 November 2020)
- FFT HDL Code Generator for Multi-Antenna mmWave Communication (18:40, 16 November 2020)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (10:39, 30 November 2020)
- Smart Patch For Heath Care And Rehabilitation (15:24, 30 November 2020)
- Matheus Cavalcante (17:33, 8 December 2020)
- Improved Reacquisition for the 5G Cellular IoT (13:04, 11 January 2021)
- ASIC Design of a Gaussian Message Passing Processor (07:34, 20 January 2021)
- ASIC Design of a Sigma Point Processor (07:34, 20 January 2021)
- Hardware Accelerator for Model Predictive Controller (07:35, 20 January 2021)
- Fast Wakeup From Deep Sleep State (07:35, 20 January 2021)
- Compressed Sensing for Wireless Biosignal Monitoring (07:35, 20 January 2021)
- Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP (07:36, 20 January 2021)
- Autoencoder Accelerator for On-Chip Semi-Supervised Learning (07:37, 20 January 2021)
- Extend the RI5CY core with priviledge extensions (07:38, 20 January 2021)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core (07:42, 20 January 2021)
- MemPool on HERO (1S) (18:07, 20 January 2021)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (18:05, 29 January 2021)
- Resilient Brain-Inspired Hyperdimensional Computing Architectures (18:08, 29 January 2021)
- Level Crossing ADC For a Many Channels Neural Recording Interface (18:10, 29 January 2021)
- RISC-V based Implementation of Secure Ranging According to IEEE 802.15.4z UWB (18:10, 29 January 2021)
- Spiking Neural Network for Autonomous Navigation (18:10, 29 January 2021)
- Event-Driven Convolutional Neural Network Modular Accelerator (18:10, 29 January 2021)
- ASIC Design Projects (18:13, 29 January 2021)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (18:19, 29 January 2021)
- A Snitch-based Compute Accelerator for HERO (M/1-2S) (22:59, 6 February 2021)
- Heroino: Design of the next CORE-V Microcontroller (23:01, 6 February 2021)
- VLSI Implementation of a 5G Ciphering Accelerator (09:05, 9 February 2021)
- OTDOA Positioning for LTE Cat-M (14:50, 9 February 2021)
- ASIC Development of 5G-NR LDPC Decoder (00:43, 10 February 2021)
- Wireless Communication Systems for the IoT (00:45, 10 February 2021)
- Software-Defined Paging in the Snitch Cluster (2-3S) (19:08, 15 February 2021)
- Event-Driven Vision on an embedded platform (07:41, 17 February 2021)
- Efficient TNN compression (07:41, 17 February 2021)
- Design and Evaluation of a Small Size Avalanche Beacon (09:02, 22 February 2021)
- ISA extensions in the Snitch Processor for Signal Processing (M) (23:08, 12 March 2021)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (14:40, 15 March 2021)
- Stand-Alone Edge Computing with GAP8 (13:38, 14 April 2021)
- Neural Networks Framwork for Embedded Plattforms (13:40, 14 April 2021)
- Ibex: Tightly-Coupled Accelerators and ISA Extensions (11:52, 27 April 2021)
- Intelligent Power Management Unit (iPMU) (10:40, 2 June 2021)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications (13:46, 2 June 2021)
- Andreas Kurth (06:40, 11 June 2021)
- Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich) (11:21, 23 June 2021)
- Integrated silicon photonic structures-Lumiphase (12:53, 23 June 2021)
- Integrated silicon photonic structures (12:58, 23 June 2021)
- Phase-change memory devices for emerging computing paradigms (13:13, 23 June 2021)
- Finite Element Simulations of Transistors for Quantum Computing (13:14, 23 June 2021)
- Manycore System on FPGA (M/S/G) (09:41, 6 July 2021)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (09:41, 6 July 2021)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (14:18, 9 July 2021)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (14:18, 9 July 2021)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (14:19, 9 July 2021)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (14:19, 9 July 2021)
- LLVM and DaCe for Snitch (1-2S) (14:20, 9 July 2021)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (14:21, 9 July 2021)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) (14:21, 9 July 2021)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S) (14:25, 9 July 2021)
- Unconventional phase change memory device concepts for in-memory and neuromorphic computin (12:07, 23 July 2021)
- Test page (11:30, 27 July 2021)
- Semi-Custom Digital VLSI for Processing-in-Memory (13:33, 28 July 2021)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G) (18:57, 29 July 2021)
- Fast Simulation of Manycore Systems (1S) (16:20, 2 August 2021)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M) (12:25, 10 August 2021)
- DC-DC Buck converter in 65nm CMOS (10:36, 20 August 2021)
- Low-Dropout Regulators for Magnetic Resonance Imaging (10:38, 20 August 2021)
- High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging (10:40, 20 August 2021)
- Ultra-low power transceiver for implantable devices (10:43, 20 August 2021)
- Inductive Charging Circuit for Implantable Devices (10:43, 20 August 2021)
- Design of a 25 Gbps SerDes for optical chip-to-chip communication (10:44, 20 August 2021)
- High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT (10:45, 20 August 2021)
- High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT (10:45, 20 August 2021)
- Design of Charge-Pump PLL in 22nm for 5G communication applications (14:51, 20 August 2021)
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich) (09:54, 31 August 2021)
- Bluetooth Low Energy network with optimized data throughput (16:18, 14 September 2021)
- A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications (14:31, 15 September 2021)
- 5G Cellular RF Front-end Design in 22nm CMOS Technology (14:36, 15 September 2021)
- Analog building blocks for mmWave manipulation (14:44, 15 September 2021)
- Low Latency Brain-Machine Interfaces (08:18, 16 September 2021)
- Hyper-Dimensional Computing Based Predictive Maintenance (08:18, 16 September 2021)
- Towards global Brain-Computer Interfaces (08:20, 16 September 2021)
- Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation (08:23, 16 September 2021)
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control (08:25, 16 September 2021)
- Every individual on the planet should have a real chance to obtain personalized medical therapy (16:04, 16 September 2021)
- Characterization techniques for silicon photonics-Lumiphase (16:05, 16 September 2021)
- Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials (16:06, 16 September 2021)
- Electrothermal characterization of van der Waals Heterostructures with a partial overlap (16:06, 16 September 2021)