User contributions
From iis-projects
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- 21:15, 23 November 2022 (diff | hist) . . (+5) . . m Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (current)
- 08:46, 11 October 2022 (diff | hist) . . (-1) . . m Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- 14:31, 15 August 2022 (diff | hist) . . (+3,280) . . N Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (Created page with "<!-- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2...")
- 13:34, 15 August 2022 (diff | hist) . . (0) . . An Efficient Compiler Backend for Snitch (1S/B) (→Character) (current)
- 13:06, 15 August 2022 (diff | hist) . . (-1) . . m High Performance SoCs (→Projects)
- 13:06, 15 August 2022 (diff | hist) . . (+1) . . m High Performance SoCs (→Available Projects)
- 13:05, 15 August 2022 (diff | hist) . . (+2,667) . . N An Efficient Compiler Backend for Snitch (1S/B) (Created page with "<!-- An Efficient Compiler Backend for Snitch (1S/B) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2022 Catego...")
- 15:19, 28 March 2022 (diff | hist) . . (+6) . . Streaming Integer Extensions for Snitch (M/1-2S)
- 23:20, 21 January 2022 (diff | hist) . . (-2) . . m Streaming Integer Extensions for Snitch (M/1-2S)
- 14:13, 6 December 2021 (diff | hist) . . (-2) . . Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
- 20:15, 19 November 2021 (diff | hist) . . (-1) . . m A Unified Compute Kernel Library for Snitch (1-2S)
- 20:15, 19 November 2021 (diff | hist) . . (+1) . . A Unified Compute Kernel Library for Snitch (1-2S)
- 20:04, 19 November 2021 (diff | hist) . . (+4,218) . . N A Unified Compute Kernel Library for Snitch (1-2S) (Created page with "<!-- Universal Stream Semantic Registers for Snitch (1S) --> Category:Digital Category:High Performance SoCs Category:Acceleration_and_Transprecision Category:2...")
- 16:39, 19 November 2021 (diff | hist) . . (-1) . . High Performance SoCs (→Projects)
- 15:29, 19 November 2021 (diff | hist) . . (-4,416) . . Integrating Hardware Accelerators into Snitch 1S (Redirected page to Integrating Hardware Accelerators into Snitch (1S)) (current)
- 15:28, 19 November 2021 (diff | hist) . . (+4,480) . . N Integrating Hardware Accelerators into Snitch (1S) (Created page with "<!-- Integrating Hardware Accelerators into Snitch (1S) --> Category:Digital Category:Acceleration_and_Transprecision Category:High Performance SoCs Category:Co...")
- 19:22, 17 November 2021 (diff | hist) . . (+2) . . Streaming Integer Extensions for Snitch (M)
- 16:32, 17 November 2021 (diff | hist) . . (-1) . . m High Performance SoCs (→Projects)
- 16:32, 17 November 2021 (diff | hist) . . (+1) . . m High Performance SoCs (→Available Projects)
- 16:32, 17 November 2021 (diff | hist) . . (+103) . . Universal Stream Semantic Registers for Snitch (1S) (Redirected page to Streaming Integer Extensions for Snitch (M)) (current)
- 16:30, 17 November 2021 (diff | hist) . . (+3,968) . . N Streaming Integer Extensions for Snitch (M) (Created page with "<!-- Universal Stream Semantic Registers for Snitch (1S) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:Acceleratio...")
- 16:03, 17 November 2021 (diff | hist) . . (+88) . . Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (→Prerequisites)
- 14:51, 17 November 2021 (diff | hist) . . (-4) . . Transforming MemPool into a CGRA (M) (current)
- 14:50, 17 November 2021 (diff | hist) . . (-2) . . Multi issue OoO Ariane Backend (M) (current)
- 14:43, 17 November 2021 (diff | hist) . . (+3,121) . . N Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (Created page with "<!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> Category:Digital Category:High Performance SoCs Category:Computer Architecture Catego...")
- 19:13, 15 November 2021 (diff | hist) . . (+3) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (→Status: Reserved)
- 19:02, 15 November 2021 (diff | hist) . . (-50) . . IP-Based SoC Generation and Configuration (1-3S/B) (→Introduction)
- 18:47, 15 November 2021 (diff | hist) . . (+766) . . IP-Based SoC Generation and Configuration (1-3S/B)
- 12:08, 15 November 2021 (diff | hist) . . (-83) . . Analog Compute-in-Memory Accelerator Interface and Integration
- 12:04, 15 November 2021 (diff | hist) . . (-1) . . High Performance SoCs (→Who are we)
- 20:35, 4 October 2021 (diff | hist) . . (+3) . . m Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- 21:18, 14 September 2021 (diff | hist) . . (-2) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- 16:03, 9 September 2021 (diff | hist) . . (-3) . . m High Performance SoCs (→Projects)
- 14:48, 9 September 2021 (diff | hist) . . (+654) . . High Performance SoCs (→Projects)
- 14:10, 10 August 2021 (diff | hist) . . (0) . . m Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (→Status: Available)
- 14:08, 10 August 2021 (diff | hist) . . (+3,465) . . N Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (Created page with "<!-- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs --> Category:Digital Category:Deep Learning Projects Category:Acceleration_and_Transp...")
- 13:52, 10 August 2021 (diff | hist) . . (+45) . . Universal Stream Semantic Registers for Snitch (1S)
- 12:25, 10 August 2021 (diff | hist) . . (+7) . . m Evaluating memory access pattern specializations in OoO, server-grade cores (M) (current)
- 12:24, 10 August 2021 (diff | hist) . . (-29) . . Universal Stream Semantic Registers for Snitch (1S)
- 12:24, 10 August 2021 (diff | hist) . . (-27) . . Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
- 10:29, 10 August 2021 (diff | hist) . . (+4,032) . . N Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (Created page with "<!-- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) --> <!-- TODO: remove safety Category:Digital Category:High Performance SoCs Category:Computer...")
- 10:27, 10 August 2021 (diff | hist) . . (+10) . . m Universal Stream Semantic Registers for Snitch (1S)
- 10:21, 10 August 2021 (diff | hist) . . (+3,205) . . N Universal Stream Semantic Registers for Snitch (1S) (Created page with "<!-- Universal Stream Semantic Registers for Snitch (1S) --> <!-- TODO: unlock safety Category:Digital Category:High Performance SoCs Category:Computer Architecture...")
- 10:07, 10 August 2021 (diff | hist) . . (+124) . . Digital (→Completed Projects)
- 18:57, 29 July 2021 (diff | hist) . . (+9) . . m SystemVerilog formatter for our LowRISC-based guidelines (2-3G) (current)
- 14:25, 9 July 2021 (diff | hist) . . (-4) . . Physical Implementation of Ara, PULP's Vector Machine (1-2S) (current)
- 14:21, 9 July 2021 (diff | hist) . . (-21) . . Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) (current)
- 14:21, 9 July 2021 (diff | hist) . . (-4) . . Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (current)
- 14:20, 9 July 2021 (diff | hist) . . (-4) . . LLVM and DaCe for Snitch (1-2S) (current)
- 14:19, 9 July 2021 (diff | hist) . . (-19) . . Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (current)
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