User contributions
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- 17:44, 15 August 2022 (diff | hist) . . (+1,047) . . MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (→Status: Available)
- 17:42, 15 August 2022 (diff | hist) . . (+395) . . MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (→Required Skills)
- 17:39, 15 August 2022 (diff | hist) . . (+12) . . MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (→Project objectives)
- 17:39, 15 August 2022 (diff | hist) . . (+1,402) . . MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (→Project description)
- 17:34, 15 August 2022 (diff | hist) . . (+2,903) . . MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (→Introduction)
- 17:26, 15 August 2022 (diff | hist) . . (+2,214) . . N MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (Created page with "==Introduction== Microcontrollers (MCUs) are used in a wide range of applications ranging from sensor-monitoring all the way to robotics. Despite typically lower in performa...")
- 17:22, 15 August 2022 (diff | hist) . . (+261) . . User:Pschiavo (→Available projects) (current)
- 17:19, 15 August 2022 (diff | hist) . . (-80) . . User:Pschiavo (→Pasquale Davide Schiavone)
- 17:08, 15 August 2022 (diff | hist) . . (+158) . . Energy Efficient SoCs
- 00:01, 7 February 2021 (diff | hist) . . (-16) . . Heroino: Design of the next CORE-V Microcontroller (→Architecture) (current)
- 00:01, 7 February 2021 (diff | hist) . . (0) . . N File:Heroino.png (current)
- 00:00, 7 February 2021 (diff | hist) . . (+52) . . Heroino: Design of the next CORE-V Microcontroller (→Architecture)
- 23:59, 6 February 2021 (diff | hist) . . (+98) . . Heroino: Design of the next CORE-V Microcontroller (→Verification)
- 23:57, 6 February 2021 (diff | hist) . . (+97) . . Heroino: Design of the next CORE-V Microcontroller (→Status: Available)
- 23:54, 6 February 2021 (diff | hist) . . (-39) . . Heroino: Design of the next CORE-V Microcontroller (→Status: Available)
- 23:53, 6 February 2021 (diff | hist) . . (-43) . . Heroino: Design of the next CORE-V Microcontroller (→Status: Available)
- 23:53, 6 February 2021 (diff | hist) . . (+2,026) . . Heroino: Design of the next CORE-V Microcontroller (→Verification)
- 23:51, 6 February 2021 (diff | hist) . . (+3,150) . . Heroino: Design of the next CORE-V Microcontroller (→Architecture)
- 23:46, 6 February 2021 (diff | hist) . . (+1,090) . . Heroino: Design of the next CORE-V Microcontroller (→Repo organization)
- 23:45, 6 February 2021 (diff | hist) . . (-7) . . Heroino: Design of the next CORE-V Microcontroller (→Repo organization)
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