User contributions
From iis-projects
- 18:49, 8 February 2021 (diff | hist) . . (+6) . . Multi issue OoO Ariane Backend (M)
- 18:48, 8 February 2021 (diff | hist) . . (-3) . . Multi issue OoO Ariane Backend (M)
- 18:32, 26 October 2020 (diff | hist) . . (+3,249) . . N Multi issue OoO Ariane Backend (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2020 Category:Master Thesis Category:Semester Thesis Category...")
- 13:39, 12 October 2020 (diff | hist) . . (+2,434) . . N SSR combined with FREP in LLVM/Clang (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2020 Category:Master Thesis Category:Semester Thesis Category...")
- 13:36, 12 October 2020 (diff | hist) . . (+2,444) . . N DaCe on Snitch (Created page with "Category:Digital Category:High Performance SoCs Category:Computer Architecture Category:2020 Category:Master Thesis Category:Semester Thesis Category...")
- 22:31, 28 September 2019 (diff | hist) . . (-57) . . Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
- 22:30, 28 September 2019 (diff | hist) . . (-57) . . Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
- 22:30, 28 September 2019 (diff | hist) . . (-71) . . Extend the RI5CY core with priviledge extensions
- 11:27, 11 December 2018 (diff | hist) . . (0) . . Trace Debugger for custom RISC-V Core (current)
- 11:26, 11 December 2018 (diff | hist) . . (-1) . . Trace Debugger for custom RISC-V Core (→Status: Available)
- 11:26, 11 December 2018 (diff | hist) . . (-23) . . Trace Debugger for custom RISC-V Core (→Status: Available)
- 18:21, 14 May 2018 (diff | hist) . . (+257) . . Extend the RI5CY core with priviledge extensions
- 12:22, 18 February 2018 (diff | hist) . . (+1) . . Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- 02:13, 30 November 2017 (diff | hist) . . (+201) . . Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration
- 17:15, 15 November 2017 (diff | hist) . . (+32) . . Creating a HDMI Video Interface for PULP
- 17:14, 15 November 2017 (diff | hist) . . (-23) . . Creating a HDMI Video Interface for PULP
- 08:52, 7 November 2017 (diff | hist) . . (+35) . . Creating a HDMI Video Interface for PULP
- 08:51, 7 November 2017 (diff | hist) . . (0) . . Trace Debugger for custom RISC-V Core (→Links)
- 08:51, 7 November 2017 (diff | hist) . . (+35) . . Trace Debugger for custom RISC-V Core
- 22:25, 4 September 2017 (diff | hist) . . (+21) . . Near-Memory Training of Neural Networks
- 22:24, 4 September 2017 (diff | hist) . . (+29) . . User:Zarubaf (→Interests) (current)
- 22:21, 4 September 2017 (diff | hist) . . (-1) . . Trace Debugger for custom RISC-V Core
- 17:02, 15 July 2017 (diff | hist) . . (+4,122) . . N Creating a HDMI Video Interface for PULP (Created page with "thumb|600px ==Introduction== At the IIS we are developing a platform for parallel ultra low power processing ([http://www.pulp-platform.org/ PULP])....")
- 16:55, 15 July 2017 (diff | hist) . . (0) . . N File:Hdmi thesis.jpg (current)
- 23:14, 5 July 2017 (diff | hist) . . (0) . . m Trace Debugger for custom RISC-V Core (Zarubaf moved page Tracer Debugger for custom RISC-V Core to Trace Debugger for custom RISC-V Core: Mis-spelled the title)
- 23:14, 5 July 2017 (diff | hist) . . (+51) . . N Tracer Debugger for custom RISC-V Core (Zarubaf moved page Tracer Debugger for custom RISC-V Core to Trace Debugger for custom RISC-V Core: Mis-spelled the title) (current)
- 23:12, 5 July 2017 (diff | hist) . . (+59) . . Trace Debugger for custom RISC-V Core
- 12:46, 5 July 2017 (diff | hist) . . (+1) . . Trace Debugger for custom RISC-V Core (→Links)
- 12:45, 5 July 2017 (diff | hist) . . (+20) . . Trace Debugger for custom RISC-V Core (→Links)
- 12:45, 5 July 2017 (diff | hist) . . (+1) . . User:Zarubaf (→Available Projects)
- 12:44, 5 July 2017 (diff | hist) . . (+121) . . User:Zarubaf
- 11:55, 5 July 2017 (diff | hist) . . (+31) . . Trace Debugger for custom RISC-V Core
- 11:54, 5 July 2017 (diff | hist) . . (0) . . N File:Debug.png (current)
- 11:51, 5 July 2017 (diff | hist) . . (+46) . . Trace Debugger for custom RISC-V Core (→Links)
- 11:51, 5 July 2017 (diff | hist) . . (-38) . . Trace Debugger for custom RISC-V Core (→Short Description)
- 11:50, 5 July 2017 (diff | hist) . . (-40) . . Trace Debugger for custom RISC-V Core
- 11:50, 5 July 2017 (diff | hist) . . (-3) . . Trace Debugger for custom RISC-V Core (→Short Description)
- 11:49, 5 July 2017 (diff | hist) . . (-28) . . Trace Debugger for custom RISC-V Core (→References)
- 11:48, 5 July 2017 (diff | hist) . . (-7) . . Trace Debugger for custom RISC-V Core (→Short Description)
- 11:47, 5 July 2017 (diff | hist) . . (0) . . Trace Debugger for custom RISC-V Core (→Short Description)
- 11:46, 5 July 2017 (diff | hist) . . (+4,972) . . N Trace Debugger for custom RISC-V Core (Created page with "Tracer Debugger for custom RISC-V Core ==Introduction== Debugging is a fundamental part of software development. It furthermore aids in bringing up silicon quickly and makes...")
- 00:24, 30 June 2017 (diff | hist) . . (+118) . . User:Zarubaf (→Florian Zaruba -- Contact Information)
- 00:22, 30 June 2017 (diff | hist) . . (+158) . . N User:Zarubaf (Created page with "==Florian Zaruba -- Contact Information== * '''e-mail''': [mailto:zarubaf@iis.ee.ethz.ch zarubaf@iis.ee.ethz.ch] Category:Supervisors Category:Digital")