Pages with the fewest revisions
From iis-projects
Showing below up to 50 results in range #51 to #100.
View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)
- Flexible Front-End Circuit for Biomedical Data Acquisition (2 revisions)
- Using Motion Sensors to Support Indoor Localization (2 revisions)
- Adaptively Controlled Hysteresis Curve Tracer For Polymer Piezoelectrics (1 S/B) (2 revisions - redirect page)
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications (2 revisions)
- Power Saver Mode for Cellular Internet of Things Receivers (2 revisions)
- Securing Block Ciphers against SCA and SIFA (2 revisions)
- Neural Architecture Search using Reinforcement Learning and Search Space Reduction (2 revisions)
- Design Review (2 revisions)
- High Throughput Turbo Decoder Design (2 revisions)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) (2 revisions)
- Weak-strong massive MIMO communication with low-resolution ADCs (2 revisions)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (2 revisions)
- LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) (2 revisions)
- Signal Acquisition and Clock Offset Compensation for High-Rate Pulse UWB PHYs (2 revisions)
- Coding Guidelines (2 revisions)
- Cryptography (2 revisions)
- Hardware Support for IDE in Multicore Environment (2 revisions)
- Design study of tunneling transistors based on a core/shell nanowire structures (2 revisions)
- Analog Layout Engine (2 revisions)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M) (2 revisions)
- Towards Self-Sustainable Unmanned Aerial Vehicles (2 revisions)
- Wearable Smart Camera With Deep Learning Algorithms For Automatic Detecion (2 revisions)
- Wireless Sensing With Long Range Comminication (LoRa) (2 revisions)
- RISC-V base ISA for ultra-low-area cores (2-3G) (2 revisions)
- SSR combined with FREP in LLVM/Clang (2 revisions)
- Computation of Phonon Bandstructure in III-V Nanostructures (2 revisions)
- Time Synchronization for 3G Mobile Communications (2 revisions)
- PULP Freertos with LLVM (2 revisions)
- Alias-Free Oscillator Synchronization for Arbitrary Waveforms (2 revisions)
- Prasadar (2 revisions)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (2 revisions)
- Neural Networks Framwork for Embedded Plattforms (2 revisions)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (2 revisions)
- Project Meetings (2 revisions)
- LightProbe - CNN-Based-Image-Reconstruction (2 revisions)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M) (2 revisions)
- Frank K. Gürkaynak (2 revisions)
- Herschmi (2 revisions)
- Optogenetics And Game Theory Applied To Small Side Bird Using Smart Sensing (2 revisions)
- VLSI Implementation Polar Decoder using High Level Synthesis (2 revisions)
- NORX - an AEAD algorithm for the CAESAR competition (2 revisions)
- Assessment of novel photovoltaic architectures by circuit simulation (2 revisions)
- Realtime Gaze Tracking on Siracusa (2 revisions)
- EvaLTE: A 2G/3G/4G Cellular Transceiver FMC (2 revisions)
- Creating A Boundry Scan Generator (1-3S/B/2-3G) (2 revisions)
- Neural Processing (2 revisions)
- Project Plan (2 revisions)
- Integrating Hardware Accelerators into Snitch 1S (2 revisions - redirect page)
- Event-based navigation on autonomous nano-drones (2 revisions)
- Simulation of Li-ion batteries and comparison with experimental data (2 revisions)