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From iis-projects
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| Date | Name | Thumbnail | Size | Description | Versions |
|---|---|---|---|---|---|
| 18:26, 29 January 2014 | Simplified trellis as used in the SOVE algorithm.png (file) |  |
617 KB | Top: Simplified trellis as used in the SOVE algorithm. Bottom: Layout of the RazorEDGE physical layer baseband ASIC. The highlighted area is occupied by the SOVE block. | 1 |
| 18:15, 29 January 2014 | Battery powered medical signal acquisition platform.png (file) |  |
481 KB | 1 | |
| 18:01, 29 January 2014 | Chip Micrograph of Cerebrov2.png (file) |  |
493 KB | Chip micrograph of the 8-channel sensor front-end and data acquisition IC ‘Cerebro v2’ for electrode-based medical applications, such as ECG or EEG. Implemented in a 130 nm CMOS technology. | 1 |
| 17:52, 29 January 2014 | Direcdt conversion receiver topology.png (file) |  |
55 KB | A direct-conversion receiver topology often used for cellular receiver, due to its good configurability. | 1 |
| 17:46, 29 January 2014 | Baseband filter transfer functions.png (file) |  |
194 KB | Measured baseband filter transfer functions, demonstrating the flat transfer function and the wide range of programmability in terms of frequency and gain. | 1 |
| 17:38, 29 January 2014 | Measured high resolution folding ADC.png (file) |  |
322 KB | Left: Measured output spectrum of a sinusoidal input signal at 60.123 MHz sampled at 150 MHz. Right: Chip micrograph of the implemented ADC in 130 nm CMOS. | 1 |
| 17:28, 29 January 2014 | Simulated spectrum of high resolution large bw.png (file) |  |
121 KB | Simulated spectrum at the output of the modulator for a sinusoidal input signal at 40MHz. | 1 |
| 18:49, 28 January 2014 | AMP OMP block diagram.png (file) |  |
118 KB | 2 | |
| 18:35, 28 January 2014 | Sandstorm layout.png (file) |  |
344 KB | 1 | |
| 18:28, 28 January 2014 | Madmax explanations.png (file) |  |
830 KB | 1 | |
| 18:16, 28 January 2014 | Warping example.png (file) |  |
528 KB | Aspect ratio retargeting example illustrating the image domain warping steps: from an initial regular grid, we generate a spatially-varying warp grid that is used to warp the image. Original image: Courtesy of Andrew Malone (CC). | 1 |
| 17:21, 28 January 2014 | Serpent high throughput.png (file) |  |
190 KB | Block diagram illustrating the OCB-Serpent architecture with four fully-unrolled Serpent cores. | 1 |
| 17:10, 28 January 2014 | 3D board of qcrypt.png (file) |  |
278 KB | This picture shows a 3D model of the new version of the PCB. All network connections are now located on the top side of the board, making it suitable for dense housing in racks. | 1 |
| 16:29, 28 January 2014 | Graestl.png (file) |  |
304 KB | Top: FPGA floorplan containing the microprocessor and the GrÆStl cryptographic co-processor. Bottom: Photo of the manufactured Chameleon chip, hosting a separate AES/Grøstl design and GrÆStl. | 1 |
| 16:11, 28 January 2014 | Share block diagram.png (file) |  |
104 KB | Simplified block diagram of the ASIP architecture, called SHAre, supporting the SHA-2 and SHA-3 hash algorithm standards. | 1 |
| 15:03, 17 January 2014 | Nanotera.gif (file) |  |
6 KB | 1 | |
| 13:39, 17 January 2014 | Ab-initio Simulation of Strained Thermoelectric Materials.jpg (file) |  |
26 KB | 1 | |
| 13:33, 17 January 2014 | Implementation of a 2-D model for Li-ion.jpg (file) |  |
38 KB | 1 | |
| 12:16, 17 January 2014 | Developing High Efficiency Batteries.jpg (file) |  |
34 KB | 1 | |
| 12:12, 17 January 2014 | Processing of 3D Micro-tomography data.jpg (file) |  |
12 KB | 1 | |
| 12:05, 17 January 2014 | Assesment of novel photovoltaic architectures.jpg (file) |  |
455 KB | 1 | |
| 11:59, 17 January 2014 | Successive Approximation Register DAC.png (file) |  |
17 KB | 1 | |
| 11:31, 17 January 2014 | Analog Layout Engine.png (file) |  |
36 KB | 1 | |
| 10:58, 17 January 2014 | Zynq Zed Board.jpg (file) |  |
76 KB | 1 | |
| 10:45, 17 January 2014 | Accelerators for object detection and tracking.jpg (file) |  |
26 KB | 1 | |
| 10:41, 17 January 2014 | Low-power chip-to-chip communication network.jpg (file) |  |
21 KB | 1 | |
| 09:45, 17 January 2014 | Power Optimization in Multipliers.jpg (file) |  |
34 KB | 1 | |
| 09:36, 17 January 2014 | Reconfigurability of SHA-3 Candidates.jpg (file) |  |
9 KB | 1 | |
| 19:13, 16 January 2014 | High-Speed DigRF-v4 Implementation.png (file) |  |
397 KB | 1 | |
| 19:10, 16 January 2014 | Channel Estimation and Equalization for LTE Advanced.jpg (file) |  |
28 KB | 1 | |
| 19:06, 16 January 2014 | Creating 3D Turbo Codes.jpg (file) |  |
40 KB | 1 | |
| 18:41, 16 January 2014 | Creating Transmitter and Testbed Development for TD-SCDMA.jpg (file) |  |
121 KB | 1 | |
| 18:27, 16 January 2014 | Creating Bandwidth Extension with Carrier Aggregation.jpg (file) |  |
76 KB | 1 | |
| 17:28, 16 January 2014 | Low Silicon Area Channel Estimation for TD-SCDMA.png (file) |  |
46 KB | 1 | |
| 17:17, 16 January 2014 | First ASIC Realization for a new HSPA.jpg (file) |  |
33 KB | 1 | |
| 17:11, 16 January 2014 | Synchronization and Power Control Concepts.jpg (file) |  |
122 KB | 1 | |
| 17:07, 16 January 2014 | Channel Estimation of 3GPP.jpg (file) |  |
142 KB | 1 | |
| 17:01, 16 January 2014 | Multiuser Equalization and Detection.jpg (file) |  |
128 KB | 1 | |
| 15:00, 16 January 2014 | Variation Tolerant.jpg (file) |  |
132 KB | 1 | |
| 13:34, 16 January 2014 | Ulp cluster cimple.png (file) |  |
14 KB | 1 |
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