List of redirects
From iis-projects
Showing below up to 50 results in range #1 to #50.
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- (M/1-2S): A Snitch-based Compute Accelerator for HERO → A Snitch-based Compute Accelerator for HERO (M/1-2S)
- 3D Turbo Coder ASIC Realization → 3D Turbo Decoder ASIC Realization
- 3D Turbo Codes → 3D Turbo Coder ASIC Realization
- 5G Cellular RF Front-end Design in 28nm CMOS Technology → 5G Cellular RF Front-end Design in 22nm CMOS Technology
- A Hardware Architecture for Real-Time Saliency Estimation → Accelerator for Spatio-Temporal Video Filtering
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks → A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- A Wireless Sensor Network for a Smart LED Lighing control → A Wireless Sensor Network for a Smart LED Lighting control
- Ab-initio Quantum Transport Simulation of Hetero-Bilayer Tunnel Field-Effect Transistors → Quantum transport in 2D heterostructures
- Ab-initio modeling of ballistic thermal transport → Integrated silicon photonic structures
- Adaptively Controlled Hysteresis Curve Tracer For Polymer Piezoelectrics (1 S/B) → Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Adaptively Controlled Hysteresis Curve Tracer For Polymer Ultrasonic Transducers (1 S/B) → Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
- Adding Linux Support to our DMA engine (1-2S/B) → Adding Linux Support to our DMA Engine (1-2S/B)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer → Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S))
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)) → Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
- Advanced Repetition Combining → Advanced 5G Repetition Combining
- All the flavours of FFT on MemPool → All the flavours of FFT on MemPool (1-2S/B)
- An FPGA-Based Testbed for 4G/LTE Mobile Communication → Baseband Processor Development for 4G IoT
- Autonomous Smart Sensors for IoT → Category:SmartSensors
- BLISS → BLISS - Battery-Less Identification System for Security
- Bateryless Imaging Neural Network → Convolutional Neural Networks in Bateryless Nodes
- Belfanti → User:Belfanti
- Bioprojects → Biomedical Circuits, Systems, and Applications
- Build the Fastest 2G Modem → Build the Fastest 2G Modem Ever
- CLIC for the CVA 6 → CLIC for the CVA6
- Cell Measurements for the Internet of Things → Cell Measurements for the 5G Internet of Things
- Channel Shortening ASIC → Channel Shortening Prefilter
- Channel Shortening Prefilter → VLSI Implementation of a Channel Shortener
- Characterization techniques for silicon photonics → Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
- Coherence-Capable Write-Back L1 Data Cache for Ariane → Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
- Configurable Ultra low power LDO → Configurable Ultra Low Power LDO
- Convolutional Network Accelerator → Design and Implementation of a Convolutional Neural Network Accelerator ASIC
- Convolutional Neural Networks in Bateryless Nodes → Gomeza old project4
- Cryogenic measurements and modeling of electrical devices → Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
- DaCe on Snitch (M/1-3S) → LLVM and DaCe for Snitch (1-2S)
- Deep-Learning Phoneme Recognition from a Ultra-Low Power Spiking Cochlea → Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
- Design and Implementation of a multi-mode multi-master I2C Interface → Design and Implementation of a multi-mode multi-master I2C peripheral
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm for 3GPP TD-HSPA → Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
- Design of Charge-Pump PLL in 28nm for 5G communication applications → Design of Charge-Pump PLL in 22nm for 5G communication applications
- Development Of A Test Bed For Ultrasonic Transducer Characterization → Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
- Digital Audio High Level Synthesis → Digital Audio High Level Synthesis for FPGAs
- Digital Audio High Level Synthesis for FPGAs → Digital Audio Processor for Cellular Applications
- Digital Beamforming ASIC for 3D Ultrasound Imaging → Digital Beamforming for Ultrasound Imaging
- Digital Front End Design for Narrowband LTE Systems → Time and Frequency Synchronization in LTE Cat-0 Devices
- Digital Transmitter Mobile Communications → Digital Transmitter for Mobile Communications
- EDGE Evolution Protocol Analyzer → Open Source Baseband Firmware for 2G Cellular Networks
- Electrical characterization and optimization of electrochemical random-access memory for analog computing → Phase-change memory devices for emerging computing paradigms
- Electron conductance of lithiated SnO2-based anode materials → Electron conductance of lithiated SnO₂ -based anode materials for Li-ion batteries
- Electron conductance of lithiated SnO₂ -based anode materials for Li-ion batteries → Stable nonvolatile resistance switching (NVRS) in single-layer 2D Materials
- Elliptic Curve Accelerator for zkSNARKS → Elliptic Curve Accelerator for zkSNARKs
- Energy Efficient AXI Inteface → Energy Efficient AXI Inteface to Analog Circuit