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Showing below up to 500 results in range #1 to #500.

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  1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
  2. 3D Matrix Multiplication Unit for ITA (1S)
  3. 3D Ultrasound Bubble Tracking
  4. 4th Generation Synchronization
  5. 5G Cellular RF Front-end Design in 22nm CMOS Technology
  6. AMZ Driverless Competition Embedded Systems Projects
  7. ASIC Design of a Gaussian Message Passing Processor
  8. ASIC Design of a Sigma Point Processor
  9. ASIC Development of 5G-NR LDPC Decoder
  10. ASIC Implementation of Jammer Mitigation
  11. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
  12. ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
  13. ASIC implementation of an interpolation-based wideband massive MIMO detector
  14. ASR-Waveformer
  15. AXI-based Network on Chip (NoC) system
  16. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
  17. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
  18. A Flexible Peripheral System for High-Performance Systems on Chip (M)
  19. A Multiview Synthesis Core in 65 nm CMOS
  20. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
  21. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
  22. A Post-Simulation Trace-Based RISC-V GDB Debugging Server
  23. A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
  24. A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
  25. A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
  26. A Snitch-based Compute Accelerator for HERO
  27. A Trustworthy Three-Factor Authentication System
  28. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  29. A Unified Compute Kernel Library for Snitch (1-2S)
  30. A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
  31. A Wearable System To Control Phone And Electronic Device Without Hands
  32. A Wearable System for long term monitoring of human physiological parameters with E skin sensors
  33. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  34. A Wireless Sensor Network for HPC monitoring
  35. A Wireless Sensor Network for a Smart Building Monitor and Control
  36. A computational memory unit using phase-change memory devices
  37. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
  38. A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
  39. Ab-initio Simulation of Strained Thermoelectric Materials
  40. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  41. Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
  42. Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
  43. Accelerators for object detection and tracking
  44. Accurate deep learning inference using computational memory
  45. Active-Set QP Solver on FPGA
  46. Advanced 5G Repetition Combining
  47. Advanced Data Movers for Modern Neural Networks
  48. Advanced EEG glasses
  49. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
  50. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
  51. Alias-Free Oscillator Synchronization for Arbitrary Waveforms
  52. Aliasing-Free Wavetable Music Synthesizer
  53. All the flavours of FFT on MemPool (1-2S/B)
  54. Ambient RF Energy harvesting for Wireless Sensor Network
  55. An Efficient Compiler Backend for Snitch (1S/B)
  56. An Energy Efficient Brain-Computer Interface using Mr.Wolf
  57. An FPGA-Based Evaluation Platform for Mobile Communications
  58. An FPGA-Based Testbed for 3G Mobile Communications Receivers
  59. An Industrial-grade Bluetooth LE Mesh Network Solution
  60. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  61. An Ultra-Low-Power Neuromorphic Spiking Neuron Design
  62. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  63. AnalogInt
  64. Analog Compute-in-Memory Accelerator Interface and Integration
  65. Analog Layout Engine
  66. Analog building blocks for mmWave manipulation
  67. Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
  68. Android Software Design
  69. Android reliability governor
  70. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
  71. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
  72. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
  73. Artificial Reverberation for Embedded Systems
  74. Assessment of novel photovoltaic architectures by circuit simulation
  75. Audio DAC Conversion Jitter Measurement System
  76. Audio Video Preprocessing In Parallel Ultra Low Power Platform
  77. Audio Visual Speech Recognition (1S/1M)
  78. Audio Visual Speech Separation (1S/1M)
  79. Audio Visual Speech Separation and Recognition (1S/1M)
  80. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  81. Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  82. Automatic unplugging detection for Ultrasound probes
  83. Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
  84. Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
  85. Autonomous Sensing For Trains In The IoT Era
  86. Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
  87. Autonomous Smart Watches: Hardware and Software Desing
  88. Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
  89. Autonomus Drones With Novel Sensors And Ultra Wide Band
  90. BCI-controlled Drone
  91. BLISS - Battery-Less Identification System for Security
  92. Bandwidth Efficient NEureka
  93. Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
  94. Bateryless Heart Rate Monitoring
  95. Battery indifferent wearable Ultrasound
  96. Beamspace processing for 5G mmWave massive MIMO on GPU
  97. Beat Cadence
  98. Beat DigRF
  99. Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
  100. Benchmarking a heterogeneous 217-core MPSoC on HPC applications
  101. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
  102. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
  103. BigPULP: Multicluster Synchronization Extensions
  104. BigPULP: Shared Virtual Memory Multicluster Extensions
  105. Big Data Analytics Benchmarks for Ara
  106. Biomedical Systems on Chip
  107. BirdGuard
  108. Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
  109. Bluetooth Low Energy network with optimized data throughput
  110. Bluetooth Low Energy receiver in 65nm CMOS
  111. Bridging QuantLab with LPDNN
  112. Bringing XNOR-nets (ConvNets) to Silicon
  113. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  114. Brunn test
  115. Build the Fastest 2G Modem Ever
  116. Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
  117. CLIC for the CVA6
  118. CMOS power amplifier for field measurements in MRI systems
  119. CPS Software-Configurable State-Machine
  120. Cell-Free mmWave Massive MIMO Communication
  121. Cell Measurements for the 5G Internet of Things
  122. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  123. Change-based Evaluation of Convolutional Neural Networks
  124. Channel Decoding for TD-HSPA
  125. Channel Estimation and Equalization for LTE Advanced
  126. Channel Estimation for 3GPP TD-SCDMA
  127. Channel Estimation for 5G Cellular IoT and Fast Fading Channels
  128. Channel Estimation for TD-HSPA
  129. Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
  130. Characterization techniques for silicon photonics-Lumiphase
  131. Charge and heat transport through graphene nanoribbon based devices
  132. Charging System for Implantable Electronics
  133. Circuits and Systems for Nanoelectrode Array Biosensors
  134. Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
  135. Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
  136. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
  137. Compiler Profiling and Optimizing
  138. Compressed Sensing Reconstruction on FPGA
  139. Compressed Sensing for Wireless Biosignal Monitoring
  140. Compression of Ultrasound data on FPGA
  141. Compression of iEEG Data
  142. Computation of Phonon Bandstructure in III-V Nanostructures
  143. Configurable Ultra Low Power LDO
  144. Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
  145. Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
  146. Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
  147. Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  148. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  149. Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  150. Covariant Feature Detector on Parallel Ultra Low Power Architecture
  151. Creating A Boundry Scan Generator (1-3S/B/2-3G)
  152. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
  153. Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
  154. Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
  155. Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
  156. Creating a HDMI Video Interface for PULP
  157. Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
  158. Cycle-Accurate Event-Based Simulation of Snitch Core
  159. DC-DC Buck converter in 65nm CMOS
  160. DaCe on Snitch
  161. Data Augmentation Techniques in Biosignal Classification
  162. Data Mapping for Unreliable Memories
  163. Deconvolution Accelerator for On-Chip Semi-Supervised Learning
  164. Deep Convolutional Autoencoder for iEEG Signals
  165. Deep Learning-based Global Local Planner for Autonomous Nano-drones
  166. Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
  167. Deep Unfolding of Iterative Optimization Algorithms
  168. Deep neural networks for seizure detection
  169. Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
  170. Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
  171. Design and Evaluation of a Small Size Avalanche Beacon
  172. Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
  173. Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
  174. Design and Implementation of a multi-mode multi-master I2C peripheral
  175. Design and Implementation of an Approximate Floating Point Unit
  176. Design and Implementation of ultra low power vision system
  177. Design and implementation of the front-end for a portable ionizing radiation detector
  178. Design of Charge-Pump PLL in 22nm for 5G communication applications
  179. Design of MEMs Sensor Interface
  180. Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
  181. Design of State Retentive Flip-Flops
  182. Design of Streaming Data Platform for High-Speed ADC Data
  183. Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
  184. Design of a 25 Gbps SerDes for optical chip-to-chip communication
  185. Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
  186. Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
  187. Design of a Fused Multiply Add Floating Point Unit
  188. Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
  189. Design of a Low Power Smart Sensing Multi-modal Vision Platform
  190. Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
  191. Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
  192. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
  193. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
  194. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
  195. Design of a VLIW processor architecture based on RISC-V
  196. Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
  197. Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
  198. Design of an LTE Module for the Internet of Things
  199. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
  200. Design of combined Ultrasound and Electromyography systems
  201. Design of combined Ultrasound and PPG systems
  202. Design of low-offset dynamic comparators
  203. Design of low mismatch DAC used for VAD
  204. Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  205. Design study of tunneling transistors based on a core/shell nanowire structures
  206. Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
  207. Designing a Power Management Unit for PULP SoCs
  208. Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
  209. Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
  210. Developing High Efficiency Batteries for Electric Cars
  211. Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
  212. Developing a small portable neutron detector for detecting smuggled nuclear material
  213. Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
  214. Development of a Rockfall Sensor Node
  215. Development of a fingertip blood pressure sensor
  216. Development of a syringe label reader for the neurocritical care unit
  217. Development of an efficient algorithm for quantum transport codes
  218. Development of an implantable Force sensor for orthopedic applications
  219. Development of statistics and contention monitoring unit for PULP
  220. DigitalUltrasoundHead
  221. Digital Audio Interface for Smart Intensive Computing Triggering
  222. Digital Control of a DC/DC Buck Converter
  223. Digital Transmitter for Cellular IoT
  224. Digitally-Controlled Analog Subtractive Sound Synthesis
  225. EEG-based drowsiness detection
  226. EEG artifact detection for epilepsy monitoring
  227. EEG artifact detection with machine learning
  228. EEG earbud
  229. Edge Computing for Long-Term Wearable Biomedical Systems
  230. Efficient Banded Matrix Multiplication for Quantum Transport Simulations
  231. Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
  232. Efficient Implementation of an Active-Set QP Solver for FPGAs
  233. Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  234. Efficient NB-IoT Uplink Design
  235. Efficient Search Design for Hyperdimensional Computing
  236. Efficient Synchronization of Manycore Systems (M/1S)
  237. Efficient TNN Inference on PULP Systems
  238. Efficient TNN compression
  239. Efficient collective communications in FlooNoC (1M)
  240. Electrothermal characterization of van der Waals Heterostructures with a partial overlap
  241. Elliptic Curve Accelerator for zkSNARKs
  242. Embedded Gesture Recognition Using Novel Mini Radar Sensors
  243. Enabling Efficient Systolic Execution on MemPool (M)
  244. Enabling Standalone Operation
  245. Enabling Standalone Operation for a Mobile Health Platform
  246. Energy-Efficient Brain-Inspired Hyperdimensional Computing
  247. Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
  248. Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
  249. Energy Efficient AXI Interface to Serial Link Physical Layer
  250. Energy Efficient Serial Link
  251. Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
  252. Energy Efficient SoCs
  253. Engineering For Kids
  254. Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
  255. Enhancing our DMA Engine with Fault Tolerance
  256. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
  257. Evaluating An Ultra low Power Vision Node
  258. Evaluating SoA Post-Training Quantization Algorithms
  259. Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
  260. Evaluating memory access pattern specializations in OoO, server-grade cores (M)
  261. Evaluating the RiscV Architecture
  262. Event-Driven Convolutional Neural Network Modular Accelerator
  263. Event-Driven Vision on an embedded platform
  264. Event-based navigation on autonomous nano-drones
  265. Every individual on the planet should have a real chance to obtain personalized medical therapy
  266. Evolved EDGE Physical Layer Incremental Redundancy Architecture
  267. Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
  268. Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
  269. Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  270. Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
  271. Exploring Algorithms for Early Seizure Detection
  272. Exploring NAS spaces with C-BRED
  273. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
  274. Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
  275. Exploring schedules for incremental and annealing quantization algorithms
  276. Extend the RI5CY core with priviledge extensions
  277. Extended Verification for Ara
  278. Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
  279. Extending our FPU with Internal High-Precision Accumulation (M)
  280. Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
  281. Extending the RISCV backend of LLVM to support PULP Extensions
  282. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
  283. Extreme-Edge Experience Replay for Keyword Spotting
  284. FFT-based Convolutional Network Accelerator
  285. FFT HDL Code Generator for Multi-Antenna mmWave Communication
  286. FPGA-Based Digital Frontend for 3G Receivers
  287. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
  288. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  289. FPGA Optimizations of Dense Binary Hyperdimensional Computing
  290. FPGA System Design for Computer Vision with Convolutional Neural Networks
  291. FPGA Testbed Implementation for Bluetooth Indoor Positioning
  292. FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  293. FPGA mapping of RPC DRAM
  294. Fast Accelerator Context Switch for PULP
  295. Fast Simulation of Manycore Systems (1S)
  296. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
  297. Fault-Tolerant Floating-Point Units (M)
  298. Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
  299. Feature Extraction for Speech Recognition (1S)
  300. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
  301. Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
  302. Finite Element Simulations of Transistors for Quantum Computing
  303. Finite element modeling of electrochemical random access memory
  304. Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
  305. Flexfloat DL Training Framework
  306. Flexible Front-End Circuit for Biomedical Data Acquisition
  307. Floating-Point Divide & Square Root Unit for Transprecision
  308. Forward error-correction ASIC using GRAND
  309. Freedom from Interference in Heterogeneous COTS SoCs
  310. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  311. GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
  312. GPT on the edge
  313. GRAND Hardware Implementation
  314. GSM Voice Capacity Evolution - VAMOS
  315. GUI-developement for an action-cam-based eye tracking device
  316. Glitches Reduce Listening Time of Your iPod
  317. Gomeza old project1
  318. Gomeza old project2
  319. Gomeza old project3
  320. Gomeza old project4
  321. Gomeza old project5
  322. Graph neural networks for epileptic seizure detection
  323. HERO: TLB Invalidation
  324. Hardware/software codesign neural decoding algorithm for “neural dust”
  325. Hardware Accelerated Derivative Pricing
  326. Hardware Acceleration
  327. Hardware Accelerator Integration into Embedded Linux
  328. Hardware Accelerator for Model Predictive Controller
  329. Hardware Constrained Neural Architechture Search
  330. Hardware Exploration of Shared-Exponent MiniFloats (M)
  331. Hardware Support for IDE in Multicore Environment
  332. Herschmi
  333. High-Resolution, Calibrated Folding ADCs
  334. High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  335. High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
  336. High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
  337. High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  338. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  339. High-speed Scene Labeling on FPGA
  340. High-throughput Embedded System For Neurotechnology in collaboration with INI
  341. High Performance Cellular Receivers in Very Advanced CMOS
  342. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  343. High Speed FPGA Trigger Logic for Particle Physics Experiments
  344. High performance continous-time Delta-Sigma ADC for biomedical applications
  345. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  346. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  347. Hyper-Dimensional Computing Based Predictive Maintenance
  348. Hyper Meccano: Acceleration of Hyperdimensional Computing
  349. Hypervisor Extension for Ariane (M)
  350. IBM A2O Core
  351. IBM Research–Zurich
  352. IP-Based SoC Generation and Configuration (1-3S)
  353. IP-Based SoC Generation and Configuration (1-3S/B)
  354. ISA extensions in the Snitch Processor for Signal Processing (1M)
  355. ISA extensions in the Snitch Processor for Signal Processing (M)
  356. Ibex: Bit-Manipulation Extension
  357. Ibex: FPGA Optimizations
  358. Ibex: Tightly-Coupled Accelerators and ISA Extensions
  359. Image Sensor Interface and Pre-processing
  360. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  361. Implementation of a 2-D model for Li-ion batteries
  362. Implementation of a Cache Reliability Mechanism (1S/M)
  363. Implementation of a Coherent Application-Class Multicore System (1-2S)
  364. Implementation of a Heterogeneous System for Image Processing on an FPGA
  365. Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  366. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  367. Implementation of an AES Hardware Processing Engine (B/S)
  368. Implementation of an Accelerator for Retentive Networks (1-2S)
  369. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
  370. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
  371. Implementing A Low-Power Sensor Node Network
  372. Implementing Configurable Dual-Core Redundancy
  373. Implementing DSP Instructions in Banshee (1S)
  374. Implementing Hibernation on the ARM Cortex M0
  375. Improved Collision Avoidance for Nano-drones
  376. Improved Reacquisition for the 5G Cellular IoT
  377. Improved State Estimation on PULP-based Nano-UAVs
  378. Improving Cold-Start in Batteryless And Energy Harvesting Systems
  379. Improving Resiliency of Hyperdimensional Computing
  380. Improving Scene Labeling with Hyperspectral Data
  381. Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
  382. Improving datarate and efficiency of ultra low power wearable ultrasound
  383. Improving our Smart Camera System
  384. In-ear EEG signal acquisition
  385. Indoor Positioning with Bluetooth
  386. Indoor Smart Tracking of Hospital instrumentation
  387. Inductive Charging Circuit for Implantable Devices
  388. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
  389. Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
  390. Infrared Wake Up Radio
  391. Integrated silicon photonic structures
  392. Integrated silicon photonic structures-Lumiphase
  393. Integrating Hardware Accelerators into Snitch
  394. Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
  395. Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
  396. Integration Of A Smart Vision System
  397. Intelligent Power Management Unit (iPMU)
  398. Interference Cancellation for EC-GSM-IoT
  399. Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC
  400. Interference Cancellation for the cellular Internet of Things
  401. Internet of Things Network Synchronizer
  402. Internet of Things SoC Characterization
  403. Investigating the Cost of Special-Case Handling in Low-Precision Floating-Point Dot Product Units (1S)
  404. Investigation of Metal Diffusion in Oxides for CBRAM Applications
  405. Investigation of Quantization Strategies for Retentive Networks (1S)
  406. Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S)
  407. Investigation of the source starvation effect in III-V MOSFET
  408. IoT Turbo Decoder
  409. Jammer-Resilient Synchronization for Wireless Communications
  410. Jammer Mitigation Meets Machine Learning
  411. Kinetic Energy Harvesting For Autonomous Smart Watches
  412. Knowledge Distillation for Embedded Machine Learning
  413. LAPACK/BLAS for FPGA
  414. LTE-Advanced RF Front-end Design in 28nm CMOS Technology
  415. LTE IoT Network Synchronization
  416. Learning Image Compression with Convolutional Networks
  417. Learning Image Decompression with Convolutional Networks
  418. Learning at the Edge with Hardware-Aware Algorithms
  419. Level Crossing ADC For a Many Channels Neural Recording Interface
  420. Libria
  421. LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project)
  422. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers
  423. LightProbe - CNN-Based-Image-Reconstruction
  424. LightProbe - Design of a High-Speed Optical Link
  425. LightProbe - Frontend Firmware and Control Side Channel
  426. LightProbe - Implementation of compressed-sensing algorithms
  427. LightProbe - Thermal-Power aware on-head Beamforming
  428. LightProbe - Ultracompact Power Supply PCB
  429. LightProbe - WIFI extension (PCB)
  430. Linux Driver for built-in ADC using DMA and Programmable Real-Time Unit (PRU) support on Beaglebone Black used as embedded HPC-performance-monitoring device
  431. Linux Driver for fine-grain and low overhead access to on-chip performance counters
  432. Low-Complexity MIMO Detection
  433. Low-Dropout Regulators for Magnetic Resonance Imaging
  434. Low-Power Time Synchronization for IoT Applications
  435. Low-Resolution 5G Beamforming Codebook Design
  436. Low-power Clock Generation Solutions for 65nm Technology
  437. Low-power Temperature-insensitive Timer
  438. Low-power chip-to-chip communication network
  439. Low-power time synchronization for IoT applications
  440. Low Latency Brain-Machine Interfaces
  441. Low Power Embedded Systems and Wireless Sensors Networks
  442. Low Power Geolocalization And Indoor Localization
  443. Low Power Neural Network For Multi Sensors Wearable Devices
  444. Low Power One bit Microphone for Acoustic Imaging Using A Parallel Processor
  445. Low Precision Ara for ML
  446. Low Resolution Neural Networks
  447. ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B)
  448. Machine Learning for extracting Muscle features from Ultrasound raw data
  449. Machine Learning for extracting Muscle features using Ultrasound
  450. Machine Learning for extracting Muscle features using Ultrasound 2
  451. Machine Learning on Ultrasound Images
  452. Main Page
  453. Make Cellular Internet of Things Receivers Smart
  454. Manycore System on FPGA (M/S/G)
  455. Mapping Networks on Reconfigurable Binary Engine Accelerator
  456. Matheus Cavalcante
  457. Mattia
  458. MemPool on HERO
  459. MemPool on HERO (1S)
  460. Memory Augmented Neural Networks in Brain-Computer Interfaces
  461. Minimal Cost RISC-V core
  462. Minimum Variance Beamforming for Wearable Ultrasound Probes
  463. Mixed-Precision Neural Networks for Brain-Computer Interface Applications
  464. Modeling FlooNoC in GVSoC (S/M)
  465. Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B)
  466. Modular Distributed Data Collection Platform
  467. Modular Frequency-Modulation (FM) Music Synthesizer
  468. Molecular Binding Kinetics Modelling of NO2 on Graphene/hBN Heterostructure
  469. Monocular Vision-based Object Following on Nano-size Robotic Blimp
  470. Moritz Schneider
  471. Multi-Band Receiver Design for LTE Mobile Communication
  472. Multisensory system for performance analysis in ski jumping (M/1-2S/B)
  473. Multiuser Equalization and Detection for 3GPP TD-SCDMA
  474. NAND Flash Open Research Platform
  475. NORX - an AEAD algorithm for the CAESAR competition
  476. NVDLA meets PULP
  477. Nanoelectrode array biosensors - programmable non-overlapping clocks generator project
  478. Nanoscale Hybrid III-V Plasmonic Laser for Low-Power Photonic ICs
  479. Near-Memory Training of Neural Networks
  480. Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA
  481. Network-off-Chip (M)
  482. Network-on-Chip for coherent and non-coherent traffic (M)
  483. Neural Architecture Search using Reinforcement Learning and Search Space Reduction
  484. Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications
  485. Neural Networks Framwork for Embedded Plattforms
  486. Neural Processing
  487. Neural Recording Interface and Signal Processing
  488. Neural Recording Interface and Spike Sorting Algorithm
  489. NeuroSoC RISC-V Component (M/1-2S)
  490. Neuromorphic Intelligence In An Embedded System in Collaboration with AiCTX
  491. Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity)
  492. NextGenChannelDec
  493. Next Generation Synchronization Signals
  494. Non-binary LDPC Decoder for Deep-Space Optical Communications
  495. Non-blocking Algorithms in Real-Time Operating Systems
  496. Novel Metastability Mitigation Technique
  497. Novel Methods for Jammer Mitigation
  498. Object Detection and Tracking on the Edge
  499. On-Board Software for PULP on a Satellite
  500. On-Device Federated Continual Learning on Nano-Drone Swarms

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