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From iis-projects
Showing below up to 50 results in range #1 to #50.
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- (hist) Deep Learning Projects [18,260 bytes]
- (hist) Human Intranet [17,908 bytes]
- (hist) Cycle-Accurate Event-Based Simulation of Snitch Core [14,727 bytes]
- (hist) Energy Efficient Autonomous UAVs [14,635 bytes]
- (hist) Feature Extraction and Architecture Clustering for Keyword Spotting (1S) [13,131 bytes]
- (hist) Transforming MemPool into a CGRA (M) [13,059 bytes]
- (hist) Resource-Constrained Few-Shot Learning for Keyword Spotting (1S) [12,726 bytes]
- (hist) Efficient Synchronization of Manycore Systems (M/1S) [12,563 bytes]
- (hist) Feature Extraction for Speech Recognition (1S) [11,915 bytes]
- (hist) A Flexible Peripheral System for High-Performance Systems on Chip (M) [11,717 bytes]
- (hist) A Snitch-based Compute Accelerator for HERO (M/1-2S) [11,101 bytes]
- (hist) LLVM and DaCe for Snitch (1-2S) [11,092 bytes]
- (hist) Audio Visual Speech Separation and Recognition (1S/1M) [11,029 bytes]
- (hist) Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) [11,007 bytes]
- (hist) Online Learning of User Features (1S) [10,895 bytes]
- (hist) High Performance SoCs [10,887 bytes]
- (hist) On-Device Learnable Embeddings for Acoustic Environments [10,834 bytes]
- (hist) Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) [10,771 bytes]
- (hist) Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) [10,534 bytes]
- (hist) PULP [10,511 bytes]
- (hist) Ultra-low power processor design [10,511 bytes]
- (hist) ASR-Waveformer [10,179 bytes]
- (hist) Implementing DSP Instructions in Banshee (1S) [10,092 bytes]
- (hist) On-Device Federated Continual Learning on Nano-Drone Swarms [10,073 bytes]
- (hist) Hyperdimensional Computing [9,993 bytes]
- (hist) Graph neural networks for epileptic seizure detection [9,773 bytes]
- (hist) Fast Simulation of Manycore Systems (1S) [9,741 bytes]
- (hist) Bringing XNOR-nets (ConvNets) to Silicon [9,740 bytes]
- (hist) Biomedical Circuits, Systems, and Applications [9,550 bytes]
- (hist) IBM Research [9,475 bytes]
- (hist) Audio Visual Speech Recognition (1S/1M) [9,414 bytes]
- (hist) Audio Visual Speech Separation (1S/1M) [9,412 bytes]
- (hist) ISA extensions in the Snitch Processor for Signal Processing (M) [9,151 bytes]
- (hist) Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea [9,139 bytes]
- (hist) Design and Implementation of a Convolutional Neural Network Accelerator ASIC [9,080 bytes]
- (hist) On - Device Continual Learning for Seizure Detection on GAP9 [9,053 bytes]
- (hist) Rethinking our Convolutional Network Accelerator Architecture [9,007 bytes]
- (hist) Extreme-Edge Experience Replay for Keyword Spotting [8,980 bytes]
- (hist) Heroino: Design of the next CORE-V Microcontroller [8,937 bytes]
- (hist) Manycore System on FPGA (M/S/G) [8,654 bytes]
- (hist) Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection [8,413 bytes]
- (hist) MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. [8,411 bytes]
- (hist) A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) [8,380 bytes]
- (hist) An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) [8,317 bytes]
- (hist) High-speed Scene Labeling on FPGA [8,302 bytes]
- (hist) Design of Scalable Event-driven Neural-Recording Digital Interface [8,231 bytes]
- (hist) A reduction-capable AXI XBAR for fast M-to-1 communication (1M) [8,184 bytes]
- (hist) FFT-based Convolutional Network Accelerator [8,120 bytes]
- (hist) Improved State Estimation on PULP-based Nano-UAVs [8,098 bytes]
- (hist) Improving our Smart Camera System [8,056 bytes]