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Showing below up to 100 results in range #51 to #150.

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  1. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)‏‎ (11 categories)
  2. BigPULP: Shared Virtual Memory Multicluster Extensions‏‎ (11 categories)
  3. Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)‏‎ (11 categories)
  4. Event-based navigation on autonomous nano-drones‏‎ (11 categories)
  5. CLIC for the CVA6‏‎ (11 categories)
  6. Fast Accelerator Context Switch for PULP‏‎ (11 categories)
  7. EEG-based drowsiness detection‏‎ (11 categories)
  8. Mixed-Precision Neural Networks for Brain-Computer Interface Applications‏‎ (11 categories)
  9. Non-blocking Algorithms in Real-Time Operating Systems‏‎ (11 categories)
  10. Predict eye movement through brain activity‏‎ (11 categories)
  11. Development of statistics and contention monitoring unit for PULP‏‎ (11 categories)
  12. Routing 1000s of wires in Network-on-Chips (1-2S/M)‏‎ (11 categories)
  13. Modeling FlooNoC in GVSoC (S/M)‏‎ (11 categories)
  14. LLVM and DaCe for Snitch (1-2S)‏‎ (11 categories)
  15. Running Rust on PULP‏‎ (11 categories)
  16. Smart e-glasses for concealed recording of EEG signals‏‎ (11 categories)
  17. EEG earbud‏‎ (11 categories)
  18. A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)‏‎ (11 categories)
  19. Evaluating SoA Post-Training Quantization Algorithms‏‎ (11 categories)
  20. In-ear EEG signal acquisition‏‎ (11 categories)
  21. A Wireless Sensor Network for HPC monitoring‏‎ (11 categories)
  22. Fault-Tolerant Floating-Point Units (M)‏‎ (11 categories)
  23. Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G)‏‎ (11 categories)
  24. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration‏‎ (11 categories)
  25. SCMI Support for Power Controller Subsystem‏‎ (11 categories)
  26. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core‏‎ (11 categories)
  27. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)‏‎ (11 categories)
  28. Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers‏‎ (11 categories)
  29. A Snitch-based Compute Accelerator for HERO (M/1-2S)‏‎ (11 categories)
  30. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)‏‎ (11 categories)
  31. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)‏‎ (11 categories)
  32. Memory Augmented Neural Networks in Brain-Computer Interfaces‏‎ (11 categories)
  33. A Flexible Peripheral System for High-Performance Systems on Chip (M)‏‎ (11 categories)
  34. Time Gain Compensation for Ultrasound Imaging‏‎ (11 categories)
  35. Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)‏‎ (11 categories)
  36. Ibex: Tightly-Coupled Accelerators and ISA Extensions‏‎ (10 categories)
  37. Smart Meters‏‎ (10 categories)
  38. Enhancing our DMA Engine with Fault Tolerance‏‎ (10 categories)
  39. Graph neural networks for epileptic seizure detection‏‎ (10 categories)
  40. Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)‏‎ (10 categories)
  41. A Unified Compute Kernel Library for Snitch (1-2S)‏‎ (10 categories)
  42. Multi issue OoO Ariane Backend (M)‏‎ (10 categories)
  43. Shared Correlation Accelerator for an RF SoC‏‎ (10 categories)
  44. Extend the RI5CY core with priviledge extensions‏‎ (10 categories)
  45. Big Data Analytics Benchmarks for Ara‏‎ (10 categories)
  46. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)‏‎ (10 categories)
  47. PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory‏‎ (10 categories)
  48. Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)‏‎ (10 categories)
  49. An FPGA-Based Testbed for 3G Mobile Communications Receivers‏‎ (10 categories)
  50. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (10 categories)
  51. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core‏‎ (10 categories)
  52. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs‏‎ (10 categories)
  53. PULPonFPGA: Lightweight Virtual Memory Support - Software Cache‏‎ (10 categories)
  54. Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)‏‎ (10 categories)
  55. Timing Channel Mitigations for RISC-V Cores‏‎ (10 categories)
  56. Fast Simulation of Manycore Systems (1S)‏‎ (10 categories)
  57. Heroino: Design of the next CORE-V Microcontroller‏‎ (10 categories)
  58. Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)‏‎ (10 categories)
  59. Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)‏‎ (10 categories)
  60. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers‏‎ (10 categories)
  61. BirdGuard‏‎ (10 categories)
  62. Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems‏‎ (10 categories)
  63. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)‏‎ (10 categories)
  64. PULP’s CLIC extensions for fast interrupt handling‏‎ (10 categories)
  65. Improving datarate and efficiency of ultra low power wearable ultrasound‏‎ (10 categories)
  66. Efficient TNN Inference on PULP Systems‏‎ (10 categories)
  67. Wireless Communication Systems for the IoT‏‎ (10 categories)
  68. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)‏‎ (10 categories)
  69. Implementing Configurable Dual-Core Redundancy‏‎ (10 categories)
  70. Taping a Safer Silicon Implementation of Snitch (M/2-3S)‏‎ (10 categories)
  71. GUI-developement for an action-cam-based eye tracking device‏‎ (10 categories)
  72. Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex‏‎ (10 categories)
  73. ASR-Waveformer‏‎ (10 categories)
  74. Accelerator for Spatio-Temporal Video Filtering‏‎ (10 categories)
  75. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)‏‎ (10 categories)
  76. Data Augmentation Techniques in Biosignal Classification‏‎ (10 categories)
  77. PULP Freertos with LLVM‏‎ (10 categories)
  78. IP-Based SoC Generation and Configuration (1-3S/B)‏‎ (10 categories)
  79. Creating A Boundry Scan Generator (1-3S/B/2-3G)‏‎ (10 categories)
  80. Ultrasound Low power WiFi with IMX7‏‎ (10 categories)
  81. Bridging QuantLab with LPDNN‏‎ (10 categories)
  82. Improved Collision Avoidance for Nano-drones‏‎ (10 categories)
  83. Softmax for Transformers (M/1-2S)‏‎ (10 categories)
  84. IoT Turbo Decoder‏‎ (10 categories)
  85. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)‏‎ (10 categories)
  86. Watchdog Timer for PULP‏‎ (10 categories)
  87. ISA extensions in the Snitch Processor for Signal Processing (M)‏‎ (10 categories)
  88. Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)‏‎ (10 categories)
  89. StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC‏‎ (10 categories)
  90. Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)‏‎ (10 categories)
  91. Machine Learning for extracting Muscle features from Ultrasound raw data‏‎ (10 categories)
  92. PULPonFPGA: Hardware L2 Cache‏‎ (10 categories)
  93. Floating-Point Divide & Square Root Unit for Transprecision‏‎ (10 categories)
  94. On-Board Software for PULP on a Satellite‏‎ (10 categories)
  95. Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications‏‎ (10 categories)
  96. Towards Formal Verification of the iDMA Engine (1-3S/B)‏‎ (10 categories)
  97. Machine Learning for extracting Muscle features using Ultrasound‏‎ (10 categories)
  98. Spatio-Temporal Video Filtering‏‎ (10 categories)
  99. Low Latency Brain-Machine Interfaces‏‎ (10 categories)
  100. Streaming Layer Normalization in ITA (M/1-2S)‏‎ (10 categories)

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