Pages with the most categories
From iis-projects
Showing below up to 250 results in range #1 to #250.
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- Wearable Ultrasound for Artery monitoring (17 categories)
- Ultrasound-EMG combined hand gesture recognition (16 categories)
- Design of combined Ultrasound and PPG systems (16 categories)
- GPT on the edge (15 categories)
- Digital (15 categories)
- Towards Flexible and Printable Wearables (15 categories)
- BigPULP: Multicluster Synchronization Extensions (14 categories)
- MCU Bus and Memory Generator: implementation of a Highly Configurable bus and memory subsystem for a RISC-V based microcontroller. (14 categories)
- Ultrasound Doppler system development (14 categories)
- Modular Distributed Data Collection Platform (14 categories)
- Testbed Design for Self-sustainable IoT Sensors (14 categories)
- FPGA mapping of RPC DRAM (13 categories)
- Battery indifferent wearable Ultrasound (13 categories)
- Advanced EEG glasses (13 categories)
- Resource Partitioning of RPC DRAM (13 categories)
- Ultra low power wearable ultrasound probe (13 categories)
- Manycore System on FPGA (M/S/G) (13 categories)
- Smart Virtual Memory Sharing (13 categories)
- Low-Energy Cluster-Coupled Vector Coprocessor for Special-Purpose PULP Acceleration (13 categories)
- Hypervisor Extension for Ariane (M) (13 categories)
- Automatic unplugging detection for Ultrasound probes (13 categories)
- Design of combined Ultrasound and Electromyography systems (13 categories)
- Design of a High-performance Hybrid PTZ for Multimodal Vision Systems (13 categories)
- Object Detection and Tracking on the Edge (13 categories)
- Design of a Low Power Smart Sensing Multi-modal Vision Platform (13 categories)
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs (13 categories)
- Transforming MemPool into a CGRA (M) (12 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB (12 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker (12 categories)
- Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models (12 categories)
- Minimum Variance Beamforming for Wearable Ultrasound Probes (12 categories)
- Efficient Synchronization of Manycore Systems (M/1S) (12 categories)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S) (12 categories)
- Real-Time ECG Contractions Classification (12 categories)
- Visualizing Functional Microbubbles using Ultrasound Imaging (12 categories)
- BCI-controlled Drone (12 categories)
- Implementing DSP Instructions in Banshee (1S) (12 categories)
- Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis (12 categories)
- Pretraining Foundational Models for EEG Signal Analysis Using Open Source Large Scale Datasets (12 categories)
- Compression of Ultrasound data on FPGA (12 categories)
- Ultrasound based hand gesture recognition (12 categories)
- Baseband Meets CPU (12 categories)
- Streaming Integer Extensions for Snitch (M/1-2S) (12 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions (12 categories)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (12 categories)
- Time Gain Compensation for Ultrasound Imaging (11 categories)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (11 categories)
- Machine Learning on Ultrasound Images (11 categories)
- Enabling Efficient Systolic Execution on MemPool (M) (11 categories)
- Real-time Linux on RISC-V (11 categories)
- Creating a HDMI Video Interface for PULP (11 categories)
- BigPULP: Shared Virtual Memory Multicluster Extensions (11 categories)
- Resource Partitioning of Caches (11 categories)
- Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B) (11 categories)
- Event-based navigation on autonomous nano-drones (11 categories)
- Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S) (11 categories)
- Fast Accelerator Context Switch for PULP (11 categories)
- CLIC for the CVA6 (11 categories)
- EEG-based drowsiness detection (11 categories)
- Mixed-Precision Neural Networks for Brain-Computer Interface Applications (11 categories)
- Non-blocking Algorithms in Real-Time Operating Systems (11 categories)
- Development of statistics and contention monitoring unit for PULP (11 categories)
- Predict eye movement through brain activity (11 categories)
- Modeling FlooNoC in GVSoC (S/M) (11 categories)
- Routing 1000s of wires in Network-on-Chips (1-2S/M) (11 categories)
- LLVM and DaCe for Snitch (1-2S) (11 categories)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B) (11 categories)
- Running Rust on PULP (11 categories)
- Smart e-glasses for concealed recording of EEG signals (11 categories)
- A Wireless Sensor Network for HPC monitoring (11 categories)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration (11 categories)
- EEG earbud (11 categories)
- Evaluating SoA Post-Training Quantization Algorithms (11 categories)
- Fault-Tolerant Floating-Point Units (M) (11 categories)
- In-ear EEG signal acquisition (11 categories)
- Towards the Ariane Desktop: Display Output for Ariane on FPGA under Linux (S/B/G) (11 categories)
- SCMI Support for Power Controller Subsystem (11 categories)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (11 categories)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (11 categories)
- A Snitch-based Compute Accelerator for HERO (M/1-2S) (11 categories)
- A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B) (11 categories)
- Training and Deploying Next-Generation Quantized Neural Networks on Microcontrollers (11 categories)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (11 categories)
- Memory Augmented Neural Networks in Brain-Computer Interfaces (11 categories)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M) (11 categories)
- Ultrasound measurement of microbubble stiffness for in situ detection of protease activity in clinical settings (10 categories)
- Zephyr RTOS on PULP (10 categories)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (10 categories)
- Streaming Layer Normalization in ITA (M/1-2S) (10 categories)
- Next Generation Synchronization Signals (10 categories)
- Deep Learning-based Global Local Planner for Autonomous Nano-drones (10 categories)
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) (10 categories)
- A Unified Compute Kernel Library for Snitch (1-2S) (10 categories)
- Ibex: Tightly-Coupled Accelerators and ISA Extensions (10 categories)
- Enhancing our DMA Engine with Fault Tolerance (10 categories)
- Smart Meters (10 categories)
- Multi issue OoO Ariane Backend (M) (10 categories)
- An FPGA-Based Testbed for 3G Mobile Communications Receivers (10 categories)
- Graph neural networks for epileptic seizure detection (10 categories)
- Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) (10 categories)
- Extend the RI5CY core with priviledge extensions (10 categories)
- Shared Correlation Accelerator for an RF SoC (10 categories)
- A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs (10 categories)
- Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B) (10 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory (10 categories)
- Big Data Analytics Benchmarks for Ara (10 categories)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S) (10 categories)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) (10 categories)
- Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S) (10 categories)
- PULPonFPGA: Lightweight Virtual Memory Support - Software Cache (10 categories)
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (10 categories)
- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) (10 categories)
- Timing Channel Mitigations for RISC-V Cores (10 categories)
- Fast Simulation of Manycore Systems (1S) (10 categories)
- LightProbe - 200G Remote DMA for GPU FPGA Data Transfers (10 categories)
- Heroino: Design of the next CORE-V Microcontroller (10 categories)
- Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S) (10 categories)
- Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M) (10 categories)
- PULP’s CLIC extensions for fast interrupt handling (10 categories)
- BirdGuard (10 categories)
- Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems (10 categories)
- Efficient TNN Inference on PULP Systems (10 categories)
- Wireless Communication Systems for the IoT (10 categories)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S) (10 categories)
- Improving datarate and efficiency of ultra low power wearable ultrasound (10 categories)
- ASR-Waveformer (10 categories)
- Accelerator for Spatio-Temporal Video Filtering (10 categories)
- Taping a Safer Silicon Implementation of Snitch (M/2-3S) (10 categories)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (10 categories)
- GUI-developement for an action-cam-based eye tracking device (10 categories)
- Implementing Configurable Dual-Core Redundancy (10 categories)
- Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex (10 categories)
- PULP Freertos with LLVM (10 categories)
- Data Augmentation Techniques in Biosignal Classification (10 categories)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (10 categories)
- Ultrasound Low power WiFi with IMX7 (10 categories)
- IP-Based SoC Generation and Configuration (1-3S/B) (10 categories)
- Creating A Boundry Scan Generator (1-3S/B/2-3G) (10 categories)
- Watchdog Timer for PULP (10 categories)
- Bridging QuantLab with LPDNN (10 categories)
- Improved Collision Avoidance for Nano-drones (10 categories)
- Softmax for Transformers (M/1-2S) (10 categories)
- IoT Turbo Decoder (10 categories)
- Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B) (10 categories)
- Machine Learning for extracting Muscle features from Ultrasound raw data (10 categories)
- ISA extensions in the Snitch Processor for Signal Processing (M) (10 categories)
- Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) (10 categories)
- StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC (10 categories)
- PULPonFPGA: Hardware L2 Cache (10 categories)
- Floating-Point Divide & Square Root Unit for Transprecision (10 categories)
- On-Board Software for PULP on a Satellite (10 categories)
- Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications (10 categories)
- Towards Formal Verification of the iDMA Engine (1-3S/B) (10 categories)
- Machine Learning for extracting Muscle features using Ultrasound (10 categories)
- Low Latency Brain-Machine Interfaces (10 categories)
- Spatio-Temporal Video Filtering (10 categories)
- Level Crossing ADC For a Many Channels Neural Recording Interface (9 categories)
- Machine Learning for extracting Muscle features using Ultrasound 2 (9 categories)
- Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) (9 categories)
- LightProbe - WIFI extension (PCB) (9 categories)
- A Multiview Synthesis Core in 65 nm CMOS (9 categories)
- Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) (9 categories)
- Advanced 5G Repetition Combining (9 categories)
- Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 M 1-2B/S) (9 categories)
- On-Device Learnable Embeddings for Acoustic Environments (9 categories)
- Improving Cold-Start in Batteryless And Energy Harvesting Systems (9 categories)
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S) (9 categories)
- Ultrasound signal processing acceleration with CUDA (9 categories)
- Outdoor Precision Object Tracking for Rockfall Experiments (9 categories)
- Hardware Constrained Neural Architechture Search (9 categories)
- System Analysis and VLSI Design of NB-IoT Baseband Processing (9 categories)
- Vector-based Parallel Programming Optimization of Communication Algorithm (1-2S/B) (9 categories)
- Coherence-Capable Write-Back L1 Data Cache for Ariane (M) (9 categories)
- Implementation of an Accelerator for Retentive Networks (1-2S) (9 categories)
- Internet of Things Network Synchronizer (9 categories)
- Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection (9 categories)
- Neural Network Algorithms and Interfaces with Accelerators for Embedded Platforms with Real World Applications (9 categories)
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels (9 categories)
- Multisensory system for performance analysis in ski jumping (M/1-2S/B) (9 categories)
- On - Device Continual Learning for Seizure Detection on GAP9 (9 categories)
- Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients (9 categories)
- Design and Implementation of an Approximate Floating Point Unit (9 categories)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust (9 categories)
- Knowledge Distillation for Embedded Machine Learning (9 categories)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (9 categories)
- Cycle-Accurate Event-Based Simulation of Snitch Core (9 categories)
- Integrating Hardware Accelerators into Snitch (1S) (9 categories)
- HERO: TLB Invalidation (9 categories)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (9 categories)
- Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) (9 categories)
- Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) (9 categories)
- EEG artifact detection for epilepsy monitoring (9 categories)
- Deep neural networks for seizure detection (9 categories)
- Autonomus Drones With Novel Sensors And Ultra Wide Band (9 categories)
- Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA (9 categories)
- Towards a Technology-independent and Synthesizable AXI4 Performance Monitoring and Throttling Unit (1-2S) (9 categories)
- EEG artifact detection with machine learning (9 categories)
- Investigation of Quantization Strategies for Retentive Networks (1S) (9 categories)
- NVDLA meets PULP (9 categories)
- Wireless EEG Acquisition and Processing (9 categories)
- Counter-based Fast Power Estimation using FPGAs (M/1-3S) (9 categories)
- AXI-based Network on Chip (NoC) system (9 categories)
- NeuroSoC RISC-V Component (M/1-2S) (9 categories)
- Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S) (9 categories)
- Ternary Neural Networks for Face Recognition (9 categories)
- Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) (9 categories)
- ML based Quantitative Movement Analysis on a Portable IoT Camera (1-2S/B) (9 categories)
- An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications (9 categories)
- Wireless In Action Data Streaming in Ski Jumping (1 B/S) (9 categories)
- BLISS - Battery-Less Identification System for Security (9 categories)
- Physics is looking for PULP (9 categories)
- Hardware/software codesign neural decoding algorithm for “neural dust” (9 categories)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations (9 categories)
- Flexfloat DL Training Framework (9 categories)
- Investigation of the high-performance multi-threaded OoO IBM A2O Core (1-3S) (9 categories)
- Real-Time Motor-Imagery Classification Using Neuromorphic Processor (9 categories)
- Trace Debugger for custom RISC-V Core (9 categories)
- Active-Set QP Solver on FPGA (9 categories)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications (9 categories)
- Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S) (9 categories)
- High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS (9 categories)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S) (9 categories)
- Learning Image Decompression with Convolutional Networks (9 categories)
- Exploring NAS spaces with C-BRED (9 categories)
- Writing a Hero runtime for EPAC (1-3S/B) (9 categories)
- Self Aware Epilepsy Monitoring (9 categories)
- MemPool on HERO (1S) (9 categories)
- Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B) (9 categories)
- Extreme-Edge Experience Replay for Keyword Spotting (9 categories)
- Probing the limits of fake-quantised neural networks (9 categories)
- High-Speed SAR ADC for next generation wireless communication in 12nm FinFET (9 categories)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) (9 categories)
- Skin Coupling Media Characterization For Fitness Tracker Applications (1 B/S) (9 categories)
- Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M) (9 categories)
- Monocular Vision-based Object Following on Nano-size Robotic Blimp (9 categories)
- An Efficient Compiler Backend for Snitch (1S/B) (9 categories)
- Learning at the Edge with Hardware-Aware Algorithms (9 categories)
- ASIC Development of 5G-NR LDPC Decoder (9 categories)
- Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) (9 categories)
- Adding Linux Support to our DMA Engine (1-2S/B) (9 categories)
- Event-Driven Convolutional Neural Network Modular Accelerator (9 categories)
- On-Device Federated Continual Learning on Nano-Drone Swarms (9 categories)
- Improved State Estimation on PULP-based Nano-UAVs (9 categories)
- Embedded Gesture Recognition Using Novel Mini Radar Sensors (8 categories)
- A reduction-capable AXI XBAR for fast M-to-1 communication (1M) (8 categories)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (8 categories)
- Ibex: FPGA Optimizations (8 categories)
- Vector-based Manycore HPC Cluster Exploration for 5G Communication Algorithm (1-2M) (8 categories)
- High-Throughput Hardware Implementations of Authenticated Encryption Algorithms (8 categories)
- Event-Driven Vision on an embedded platform (8 categories)
