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Showing below up to 50 results in range #101 to #150.

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  1. Extend the RI5CY core with priviledge extensions‏‎ (10 categories)
  2. Shared Correlation Accelerator for an RF SoC‏‎ (10 categories)
  3. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs‏‎ (10 categories)
  4. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)‏‎ (10 categories)
  5. PULPonFPGA: Lightweight Virtual Memory Support - Physically Contiguous Memory‏‎ (10 categories)
  6. Big Data Analytics Benchmarks for Ara‏‎ (10 categories)
  7. Physical Implementation of Ara, PULP's Vector Machine (1-2S)‏‎ (10 categories)
  8. Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)‏‎ (10 categories)
  9. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)‏‎ (10 categories)
  10. PULPonFPGA: Lightweight Virtual Memory Support - Software Cache‏‎ (10 categories)
  11. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core‏‎ (10 categories)
  12. Timing Channel Mitigations for RISC-V Cores‏‎ (10 categories)
  13. Fast Simulation of Manycore Systems (1S)‏‎ (10 categories)
  14. Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)‏‎ (10 categories)
  15. Heroino: Design of the next CORE-V Microcontroller‏‎ (10 categories)
  16. Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)‏‎ (10 categories)
  17. Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)‏‎ (10 categories)
  18. LightProbe - 200G Remote DMA for GPU FPGA Data Transfers‏‎ (10 categories)
  19. PULP’s CLIC extensions for fast interrupt handling‏‎ (10 categories)
  20. BirdGuard‏‎ (10 categories)
  21. Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems‏‎ (10 categories)
  22. Efficient TNN Inference on PULP Systems‏‎ (10 categories)
  23. Wireless Communication Systems for the IoT‏‎ (10 categories)
  24. Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)‏‎ (10 categories)
  25. Improving datarate and efficiency of ultra low power wearable ultrasound‏‎ (10 categories)
  26. ASR-Waveformer‏‎ (10 categories)
  27. Accelerator for Spatio-Temporal Video Filtering‏‎ (10 categories)
  28. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)‏‎ (10 categories)
  29. GUI-developement for an action-cam-based eye tracking device‏‎ (10 categories)
  30. Implementing Configurable Dual-Core Redundancy‏‎ (10 categories)
  31. Taping a Safer Silicon Implementation of Snitch (M/2-3S)‏‎ (10 categories)
  32. Real-Time Embedded Classification of Neural Activity in Rat Barrel Cortex‏‎ (10 categories)
  33. PULP Freertos with LLVM‏‎ (10 categories)
  34. Data Augmentation Techniques in Biosignal Classification‏‎ (10 categories)
  35. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)‏‎ (10 categories)
  36. Ultrasound Low power WiFi with IMX7‏‎ (10 categories)
  37. IP-Based SoC Generation and Configuration (1-3S/B)‏‎ (10 categories)
  38. Creating A Boundry Scan Generator (1-3S/B/2-3G)‏‎ (10 categories)
  39. Watchdog Timer for PULP‏‎ (10 categories)
  40. Bridging QuantLab with LPDNN‏‎ (10 categories)
  41. Improved Collision Avoidance for Nano-drones‏‎ (10 categories)
  42. Softmax for Transformers (M/1-2S)‏‎ (10 categories)
  43. IoT Turbo Decoder‏‎ (10 categories)
  44. Machine Learning for extracting Muscle features from Ultrasound raw data‏‎ (10 categories)
  45. ISA extensions in the Snitch Processor for Signal Processing (M)‏‎ (10 categories)
  46. Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)‏‎ (10 categories)
  47. StoneEDGE: An EC-GSM-IoT and Evolved EDGE PHY ASIC‏‎ (10 categories)
  48. Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)‏‎ (10 categories)
  49. PULPonFPGA: Hardware L2 Cache‏‎ (10 categories)
  50. Floating-Point Divide & Square Root Unit for Transprecision‏‎ (10 categories)

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