Search results

Create the page "Accelerator" on this wiki! See also the search results found.

Page title matches

• Accelerator for Spatio-Temporal Video Filtering
  3 KB (366 words) - 12:40, 1 June 2017
• Accelerator for Boosted Binary Features
  3 KB (373 words) - 11:51, 19 August 2017
• Hardware Accelerator Integration into Embedded Linux
  ...ffloaded to accelerators to allow for a more efficient execution. One such accelerator determined to solve Gaussian Message Passing algorithms in an efficient way ...he accelerator. At the end of the project, you will be able to control the accelerator from the command line of the Linux system.
  2 KB (236 words) - 09:46, 12 October 2017
• Hardware Accelerator for Model Predictive Controller
  [[File:Hardware Accelerator for Model Predictive Controller1.png|400px|thumb]] [[File:Hardware Accelerator for Model Predictive Controller2.png|400px|thumb]]
  3 KB (456 words) - 08:35, 20 January 2021
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  ...to 90%). The focus of this work is on speeding up this step by creating an accelerator to perform this step faster and more power-efficiently. ...t-yet-published paper of our group by F. Conti and L. Benini on a hardware-accelerator for ConvNets
  9 KB (1,289 words) - 19:45, 24 March 2015
• Convolutional Network Accelerator
  #REDIRECT [[Design and Implementation of a Convolutional Neural Network Accelerator ASIC]]
  90 bytes (11 words) - 12:55, 13 December 2014
• FFT-based Convolutional Network Accelerator
  ...focus of this work is on speeding up this step by creating an ASIC or FPGA accelerator to perform this step faster and more power-efficiently in the frequency dom
  8 KB (1,145 words) - 11:30, 5 February 2016
• Rethinking our Convolutional Network Accelerator Architecture
  ...e time is spent performing the convolutions (80% to 90%). We have built an accelerator for this, Origami, which has been very successful. Nevertheless, it has som ...Samuel Willi, Beat Muheim, Luca Benini, "Origami: A Convolutional Network Accelerator", Proc. ACM/IEEE GLS-VLSI'15 [http://dl.acm.org/citation.cfm?id=2743766] [h
  9 KB (1,263 words) - 18:52, 12 December 2016
• Deconvolution Accelerator for On-Chip Semi-Supervised Learning
  0 bytes (0 words) - 14:48, 30 May 2017
• Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  In this thesis, the students will develop an optimized Deconvolution Accelerator which can be used to implement state-of-the-art neural networks with a deco
  6 KB (842 words) - 08:37, 20 January 2021
• Shared Correlation Accelerator for an RF SoC
  ...cated circuit for each standard, we would like to share a single, flexible accelerator for all these tasks. [[File:Correlation acc.png|450px|thumb|Concept for the shared correlation accelerator.]]
  3 KB (421 words) - 09:38, 14 September 2018
• Analog Compute-in-Memory Accelerator Interface and Integration
  ...ices can be exploited as the basic cell of analog compute-in-memory (AciM) accelerator for MAC operation that can significantly outperform the current state-of-th ...ject is to design the interface for the ACiM accelerator and integrate the accelerator into a modern microcontroller system.
  3 KB (352 words) - 18:02, 16 December 2022
• Elliptic Curve Accelerator for zkSNARKs
  ...In this project you would investigate the feasibility of an elliptic curve accelerator for the specific curves used in ZCash. You will devise an optimal architect
  5 KB (614 words) - 15:02, 4 March 2019
• Elliptic Curve Accelerator for zkSNARKS
  #REDIRECT [[Elliptic Curve Accelerator for zkSNARKs]]
  53 bytes (6 words) - 10:18, 24 August 2018
• Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
  ...e. The new L1 interconnect will be tested together with a state-of-the-art accelerator for Binary Neural Networks, constituting a very important component for for ...n a field of active exciting research to develop a state-of-art inference accelerator for MPSoC and FPGA targets. You will learn:
  7 KB (961 words) - 21:21, 29 January 2019
• Event-Driven Convolutional Neural Network Modular Accelerator
  ...to use, and in the number of physical computing engines instantiated. The accelerator operations are orchestrated by an RISCV core programmed through a JTAG inte
  4 KB (651 words) - 19:10, 29 January 2021
• Mapping Networks on Reconfigurable Binary Engine Accelerator
  ...orks NEMO [2] (or Quantlab [3]) and DORY[4,5] to map networks onto the RBE accelerator and evaluate their performance and energy efficiency for real networks. The RBE accelerator consists out of three parts:
  6 KB (814 words) - 09:55, 8 March 2023
• An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  ...this projet is the development of a hardware matrix-vector multiplication accelerator that solely relies on standard cells as state holding elements of the desig ...will have the oportunity to tapeout the microcontroller including your HW accelerator as part of a TSMC65nm multi-project-waver (MPW) run, which will give you pr
  7 KB (1,032 words) - 15:31, 16 November 2020
• A Snitch-based Compute Accelerator for HERO
  0 bytes (0 words) - 14:58, 29 July 2020
• (M/1-2S): A Snitch-based Compute Accelerator for HERO
  #Redirect [[A Snitch-based Compute Accelerator for HERO (M/1-2S)]]
  66 bytes (10 words) - 21:47, 10 November 2020

Page text matches

• Accelerators for object detection and tracking
  In this project, you will design a hardware accelerator for image system, improving the energy efficiency of the system. The accelerator will
  3 KB (407 words) - 10:57, 5 November 2019
• Pirmin Vogel
  ...river, runtime and programming model support for efficient and transparent accelerator programming.
  1 KB (193 words) - 15:39, 3 March 2020
• MatPHY: An Open-Source Physical Layer Development Framework
  ...eiver that is typically implemented on the baseband processor, assisted by accelerator blocks in dedicated hardware including TPU, digital frontend, detector and
  3 KB (360 words) - 14:14, 27 May 2015
• Evolved EDGE Physical Layer Incremental Redundancy Architecture
  ...the RLC blocks takes place on a PHY Digital Signal Processor (DSP) and an accelerator attached to it.
  3 KB (397 words) - 14:12, 27 May 2015
• Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  ...rm. After verifying correct functionality, you will integrate the complete accelerator inside the PULP platform (either in the simulation platform or the FPGA emu ...field of active exciting research to develop a state-of-art neuromorphic accelerator for MPSoC and FPGA targets. You will learn:
  5 KB (784 words) - 14:50, 30 November 2016
• Hardware Accelerator Integration into Embedded Linux
  ...ffloaded to accelerators to allow for a more efficient execution. One such accelerator determined to solve Gaussian Message Passing algorithms in an efficient way ...he accelerator. At the end of the project, you will be able to control the accelerator from the command line of the Linux system.
  2 KB (236 words) - 09:46, 12 October 2017
• PULP
  ...alized in 28nm FDSOI (RVT) technology with 4 parallel cores and a hardware accelerator. * [http://asic.ethz.ch/2021/Echoes.html Echoes] PULPissimo system with FFT accelerator, new peripherals and for the first time CV32E40P core.
  10 KB (1,563 words) - 10:09, 19 August 2022
• Hardware Accelerator for Model Predictive Controller
  [[File:Hardware Accelerator for Model Predictive Controller1.png|400px|thumb]] [[File:Hardware Accelerator for Model Predictive Controller2.png|400px|thumb]]
  3 KB (456 words) - 08:35, 20 January 2021
• ASIC Design of a Sigma Point Processor
  ...ication specific processors of this type are serve as an signal-processing accelerator in heterogeneous multicore processors. They offer a unique blend of flexibi
  2 KB (265 words) - 08:34, 20 January 2021
• Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  ...to 90%). The focus of this work is on speeding up this step by creating an accelerator to perform this step faster and more power-efficiently. ...t-yet-published paper of our group by F. Conti and L. Benini on a hardware-accelerator for ConvNets
  9 KB (1,289 words) - 19:45, 24 March 2015
• Hardware/software co-programming on the Parallella platform
  all available computation resources like CPU, accelerator chip and FPGA. ...a dual-core ARM A9 processor running Linux, a powerful FPGA and a 16-core accelerator chip called "Epiphany III". All these components cores are linked tightly t
  3 KB (501 words) - 14:26, 2 September 2015
• Convolutional Network Accelerator
  #REDIRECT [[Design and Implementation of a Convolutional Neural Network Accelerator ASIC]]
  90 bytes (11 words) - 12:55, 13 December 2014
• Active-Set QP Solver on FPGA
  ...focus on the implementation of an Active-Set quadratic program (QP) solver accelerator on FPGA. ...ory:Digital]] [[Category:Master Thesis]] [[Category:Completed]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Cont
  2 KB (351 words) - 13:09, 2 November 2015
• LAPACK/BLAS for FPGA
  [[[Category:Digital]] [[Category:Master Thesis]] [[Category:Accelerator]] [[Category:FPGA]] [[Category:ABB CHCRC]] [[Category:Model Predictive Cont
  2 KB (328 words) - 12:38, 1 June 2017
• Real-Time Stereo to Multiview Conversion
  dedicated hardware accelerator enables portable and energy would serve as a power-efficient hardware accelerator.
  3 KB (509 words) - 09:09, 23 October 2015
• Acceleration and Transprecision
  ...A Tesla V100.jpg|thumb|right|A NVIDIA Tesla V100 GP-GPU. This cutting-edge accelerator provides huge computational power on a [https://arstechnica.com/gadgets/201 ...b|right|Google's Cloud TPU (Tensor Processing Unit). This machine learning accelerator can do one thing extremely well: multiply-accumulate operations.]]
  2 KB (275 words) - 17:05, 24 November 2023
• PULPonFPGA: Lightweight Virtual Memory Support - Software Cache
  ...requires the programmer to manually orchestrate DMA transfers between the accelerator's low latency tightly-coupled data memory (TCDM), an L1 scratchpad memory, ...h a software cache similar to [5] that uses part of the TCDM to filter the accelerator's accesses to shared data structures living in main memory, and to spare th
  5 KB (716 words) - 13:43, 29 November 2019
• FFT-based Convolutional Network Accelerator
  ...focus of this work is on speeding up this step by creating an ASIC or FPGA accelerator to perform this step faster and more power-efficiently in the frequency dom
  8 KB (1,145 words) - 11:30, 5 February 2016
• PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions
  ...ort the accelerator coherency port (ACP) of the Zynq SoC, which allows the accelerator to access the low-latency on-chip memories of the host including L1 and L2 : 10% User-space Runtime and Application Development for Host and Accelerator
  4 KB (585 words) - 17:57, 7 November 2017
• Optimization of a Binary Feature Extraction Core using Approximation
  #REDIRECT [[Accelerator for Boosted Binary Features]]
  53 bytes (6 words) - 18:14, 14 April 2016

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)