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Showing below up to 20 results in range #1 to #20.

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1. (hist) ‎Deconvolution Accelerator for On-Chip Semi-Supervised Learning ‎[0 bytes]
2. (hist) ‎Neural Processing ‎[0 bytes]
3. (hist) ‎Near-Memory Training of Neural Networks ‎[0 bytes]
4. (hist) ‎Biomedical System on Chips ‎[0 bytes]
5. (hist) ‎Mattia ‎[0 bytes]
6. (hist) ‎Enabling Standalone Operation ‎[0 bytes]
7. (hist) ‎Optimal System Duty Cycling ‎[0 bytes]
8. (hist) ‎Implementation of a Heterogeneous System for Image Processing on an FPGA ‎[0 bytes]
9. (hist) ‎Palm size chip NMR ‎[0 bytes]
10. (hist) ‎A Snitch-based Compute Accelerator for HERO ‎[0 bytes]
11. (hist) ‎(M): A Flexible Peripheral System for High-Performance Systems on Chip ‎[0 bytes]
12. (hist) ‎IBM Research–Zurich ‎[0 bytes]
13. (hist) ‎DaCe on Snitch ‎[0 bytes]
14. (hist) ‎SSR combined with FREP in LLVM/Clang ‎[0 bytes]
15. (hist) ‎IBM A2O Core ‎[0 bytes]
16. (hist) ‎IP-Based SoC Generation and Configuration (1-3S) ‎[0 bytes]
17. (hist) ‎MemPool on HERO ‎[0 bytes]
18. (hist) ‎ISA extensions in the Snitch Processor for Signal Processing (1M) ‎[0 bytes]
19. (hist) ‎Integrating Hardware Accelerators into Snitch ‎[0 bytes]
20. (hist) ‎Prasadar ‎[0 bytes]

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