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From iis-projects
Showing below up to 250 results in range #1 to #250.
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- (hist) Deconvolution Accelerator for On-Chip Semi-Supervised Learning [0 bytes]
- (hist) Neural Processing [0 bytes]
- (hist) Near-Memory Training of Neural Networks [0 bytes]
- (hist) Biomedical System on Chips [0 bytes]
- (hist) Mattia [0 bytes]
- (hist) Enabling Standalone Operation [0 bytes]
- (hist) Optimal System Duty Cycling [0 bytes]
- (hist) Implementation of a Heterogeneous System for Image Processing on an FPGA [0 bytes]
- (hist) Palm size chip NMR [0 bytes]
- (hist) A Snitch-based Compute Accelerator for HERO [0 bytes]
- (hist) (M): A Flexible Peripheral System for High-Performance Systems on Chip [0 bytes]
- (hist) IBM Research–Zurich [0 bytes]
- (hist) DaCe on Snitch [0 bytes]
- (hist) SSR combined with FREP in LLVM/Clang [0 bytes]
- (hist) IBM A2O Core [0 bytes]
- (hist) IP-Based SoC Generation and Configuration (1-3S) [0 bytes]
- (hist) MemPool on HERO [0 bytes]
- (hist) ISA extensions in the Snitch Processor for Signal Processing (1M) [0 bytes]
- (hist) Integrating Hardware Accelerators into Snitch [0 bytes]
- (hist) Prasadar [0 bytes]
- (hist) On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks [0 bytes]
- (hist) Test project [0 bytes]
- (hist) Benchmarking a heterogeneous 217-core MPSoC on HPC applications [0 bytes]
- (hist) Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) [0 bytes]
- (hist) A Post-Simulation Trace-Based RISC-V GDB Debugging Server [0 bytes]
- (hist) Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) [0 bytes]
- (hist) Versatile HW SW Digital PHY for inter chip communication [0 bytes]
- (hist) Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) [0 bytes]
- (hist) Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) [0 bytes]
- (hist) Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) [0 bytes]
- (hist) Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) [0 bytes]
- (hist) Test page [16 bytes]
- (hist) A Trustworthy Three-Factor Authentication System [40 bytes]
- (hist) Influence of the Initial FilamentGeometry on the Forming Step in CBRAM [75 bytes]
- (hist) Theory, Algorithms, and Hardware for Beyond 5G [120 bytes]
- (hist) Positioning with Wireless Signals [121 bytes]
- (hist) All-Digital In-Memory Processing [121 bytes]
- (hist) Real-Time Optimization [121 bytes]
- (hist) Audio Signal Processing [123 bytes]
- (hist) Simultaneous Sensing and Communication [123 bytes]
- (hist) Mixed-Signal Circuit Design [123 bytes]
- (hist) Analog IC Design [130 bytes]
- (hist) Mixed Signal IC Design [136 bytes]
- (hist) AnalogInt [343 bytes]
- (hist) Atretter [362 bytes]
- (hist) Tbenz [362 bytes]
- (hist) Audio [403 bytes]
- (hist) Taimir Aguacil [416 bytes]
- (hist) Christoph Keller [423 bytes]
- (hist) Project Meetings [425 bytes]
- (hist) Project Plan [453 bytes]
- (hist) Moritz Schneider [459 bytes]
- (hist) Software [473 bytes]
- (hist) Stefan Lippuner [532 bytes]
- (hist) Benjamin Sporrer [567 bytes]
- (hist) Philipp Schönle [569 bytes]
- (hist) Design Review [577 bytes]
- (hist) Nils Wistoff [578 bytes]
- (hist) Mauro Salomon [637 bytes]
- (hist) Cryptography [645 bytes]
- (hist) Libria [646 bytes]
- (hist) Karim Badawi [653 bytes]
- (hist) Matthias Korb [698 bytes]
- (hist) Energy Efficient Circuits and IoT Systems Group [736 bytes]
- (hist) EECIS [740 bytes]
- (hist) Harald Kröll [764 bytes]
- (hist) Pascal Hager [775 bytes]
- (hist) Research [789 bytes]
- (hist) Ultrasound [797 bytes]
- (hist) Federico Villani [834 bytes]
- (hist) Coding Guidelines [841 bytes]
- (hist) Herschmi [859 bytes]
- (hist) Matheus Cavalcante [890 bytes]
- (hist) Telecommunications [892 bytes]
- (hist) Benjamin Weber [894 bytes]
- (hist) Norbert Felber [897 bytes]
- (hist) Christoph Leitner [928 bytes]
- (hist) Robert Balas [931 bytes]
- (hist) GRAND Hardware Implementation [990 bytes]
- (hist) FPGA [1,020 bytes]
- (hist) Matteo Perotti [1,028 bytes]
- (hist) Andreas Kurth [1,029 bytes]
- (hist) Fabian Schuiki [1,031 bytes]
- (hist) Stefan Mach [1,044 bytes]
- (hist) Eye tracking [1,058 bytes]
- (hist) Integrated Devices, Electronics, And Systems [1,058 bytes]
- (hist) Frank K. Gürkaynak [1,072 bytes]
- (hist) Low-Power Time Synchronization for IoT Applications [1,085 bytes]
- (hist) Physical Layer Implementation of HSPA+ 4G Mobile Transceiver [1,088 bytes]
- (hist) Guillaume Mocquard [1,117 bytes]
- (hist) Final Presentation [1,130 bytes]
- (hist) Channel Estimation for 3GPP TD-SCDMA [1,144 bytes]
- (hist) Synchronization and Power Control Concepts for 3GPP TD-SCDMA [1,145 bytes]
- (hist) Michael Muehlberghuber [1,160 bytes]
- (hist) An FPGA-Based Testbed for 3G Mobile Communications Receivers [1,168 bytes]
- (hist) FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications [1,194 bytes]
- (hist) Michael Rogenmoser [1,211 bytes]
- (hist) Interference Cancellation for EC-GSM-IoT [1,281 bytes]
- (hist) Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) [1,284 bytes]
- (hist) ASIC [1,286 bytes]
- (hist) PREM on PULP [1,304 bytes]
- (hist) Configurable Ultra Low Power LDO [1,306 bytes]
- (hist) Exploring Algorithms for Early Seizure Detection [1,329 bytes]
- (hist) SW/HW Predictability and Security [1,333 bytes]
- (hist) Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) [1,378 bytes]
- (hist) Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) [1,408 bytes]
- (hist) Design of low mismatch DAC used for VAD [1,409 bytes]
- (hist) Scan Chain Fault Injection in a PULP SoC (1S) [1,421 bytes]
- (hist) Receiver design for the DigRF 4G high speed serial link [1,431 bytes]
- (hist) Beat Cadence [1,442 bytes]
- (hist) Precise Ultra-low-power Timer [1,446 bytes]
- (hist) Digital Audio Processor for Cellular Applications [1,448 bytes]
- (hist) Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) [1,466 bytes]
- (hist) Multiuser Equalization and Detection for 3GPP TD-SCDMA [1,484 bytes]
- (hist) Creating A Boundry Scan Generator (1-3S/B/2-3G) [1,488 bytes]
- (hist) Design of a D-Band Variable Gain Amplifier for 6G Communication [1,522 bytes]
- (hist) Positioning for the cellular Internet of Things [1,525 bytes]
- (hist) ASIC Design of a Gaussian Message Passing Processor [1,526 bytes]
- (hist) Pirmin Vogel [1,528 bytes]
- (hist) Novel Metastability Mitigation Technique [1,561 bytes]
- (hist) High resolution, low power Sigma Delta ADC [1,568 bytes]
- (hist) Marco Bertuletti [1,571 bytes]
- (hist) Hardware Accelerator Integration into Embedded Linux [1,578 bytes]
- (hist) LightProbe - CNN-Based-Image-Reconstruction [1,582 bytes]
- (hist) Hardware Support for IDE in Multicore Environment [1,591 bytes]
- (hist) Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) [1,597 bytes]
- (hist) Ultrasound signal processing acceleration with CUDA [1,600 bytes]
- (hist) Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) [1,645 bytes]
- (hist) Synchronisation and Cyclic Prefix Handling For LTE Testbed [1,649 bytes]
- (hist) Audio Video Preprocessing In Parallel Ultra Low Power Platform [1,650 bytes]
- (hist) Fast Wakeup From Deep Sleep State [1,665 bytes]
- (hist) Fault Tolerance [1,665 bytes]
- (hist) EvaLTE: A 2G/3G/4G Cellular Transceiver FMC [1,679 bytes]
- (hist) Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) [1,705 bytes]
- (hist) GSM Voice Capacity Evolution - VAMOS [1,707 bytes]
- (hist) Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) [1,722 bytes]
- (hist) Design and Implementation of a multi-mode multi-master I2C peripheral [1,729 bytes]
- (hist) Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) [1,729 bytes]
- (hist) System Analysis and VLSI Design of NB-IoT Baseband Processing [1,736 bytes]
- (hist) Toward Superposition of Brain-Computer Interface Models [1,758 bytes]
- (hist) State-Saving @ NXP [1,767 bytes]
- (hist) Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) [1,776 bytes]
- (hist) Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) [1,794 bytes]
- (hist) Power Saver Mode for Cellular Internet of Things Receivers [1,795 bytes]
- (hist) Bluetooth Low Energy receiver in 65nm CMOS [1,795 bytes]
- (hist) Adding Linux Support to our DMA Engine (1-2S/B) [1,795 bytes]
- (hist) LTE-Advanced RF Front-end Design in 28nm CMOS Technology [1,811 bytes]
- (hist) 5G Cellular RF Front-end Design in 22nm CMOS Technology [1,818 bytes]
- (hist) AXI-based Network on Chip (NoC) system [1,825 bytes]
- (hist) Energy Efficient Serial Link [1,833 bytes]
- (hist) LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) [1,841 bytes]
- (hist) Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets [1,852 bytes]
- (hist) Open Source Baseband Firmware for 2G Cellular Networks [1,858 bytes]
- (hist) Interference Cancellation for the cellular Internet of Things [1,860 bytes]
- (hist) Bluetooth Low Energy network with optimized data throughput [1,860 bytes]
- (hist) Ultrasound Low power WiFi with IMX7 [1,861 bytes]
- (hist) Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets [1,863 bytes]
- (hist) Fast and Accurate Multiclass Inference for Brain–Computer Interfaces [1,865 bytes]
- (hist) Low-Dropout Regulators for Magnetic Resonance Imaging [1,867 bytes]
- (hist) Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) [1,878 bytes]
- (hist) Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf [1,896 bytes]
- (hist) Implementation of a Coherent Application-Class Multicore System (1-2S) [1,897 bytes]
- (hist) Multi-Band Receiver Design for LTE Mobile Communication [1,907 bytes]
- (hist) LightProbe [1,907 bytes]
- (hist) Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA [1,914 bytes]
- (hist) Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) [1,929 bytes]
- (hist) Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen [1,931 bytes]
- (hist) Enabling Standalone Operation for a Mobile Health Platform [1,934 bytes]
- (hist) Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC [1,946 bytes]
- (hist) GUI-developement for an action-cam-based eye tracking device [1,949 bytes]
- (hist) High Performance Cellular Receivers in Very Advanced CMOS [1,952 bytes]
- (hist) Make Cellular Internet of Things Receivers Smart [1,954 bytes]
- (hist) Towards Formal Verification of the iDMA Engine (1-3S/B) [1,954 bytes]
- (hist) Non-binary LDPC Decoder for Deep-Space Optical Communications [1,958 bytes]
- (hist) Jammer-Resilient Synchronization for Wireless Communications [1,962 bytes]
- (hist) Wireless Biomedical Signal Acquisition Device [1,982 bytes]
- (hist) 3D Ultrasound Bubble Tracking [1,982 bytes]
- (hist) RazorEDGE: An Evolved EDGE DBB ASIC [1,995 bytes]
- (hist) Implementation of a Cache Reliability Mechanism (1S/M) [1,996 bytes]
- (hist) ASIC Design of a Sigma Point Processor [1,998 bytes]
- (hist) Beat DigRF [2,000 bytes]
- (hist) Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening [2,001 bytes]
- (hist) Energy Efficient AXI Interface to Serial Link Physical Layer [2,020 bytes]
- (hist) High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS [2,024 bytes]
- (hist) Signal to Noise Ratio Estimation for 3G standards [2,025 bytes]
- (hist) Channel Estimation for TD-HSPA [2,028 bytes]
- (hist) Event-Driven Computing [2,043 bytes]
- (hist) Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC [2,044 bytes]
- (hist) Acceleration and Transprecision [2,054 bytes]
- (hist) Implementation of an AES Hardware Processing Engine (B/S) [2,064 bytes]
- (hist) Analog building blocks for mmWave manipulation [2,064 bytes]
- (hist) Intelligent Power Management Unit (iPMU) [2,067 bytes]
- (hist) Compression of Ultrasound data on FPGA [2,067 bytes]
- (hist) Predictable Execution [2,068 bytes]
- (hist) Machine Learning on Ultrasound Images [2,071 bytes]
- (hist) Design of a Digital Audio Module for Ultra-Low Power Cellular Applications [2,072 bytes]
- (hist) Improving Resiliency of Hyperdimensional Computing [2,073 bytes]
- (hist) Audio DAC Conversion Jitter Measurement System [2,075 bytes]
- (hist) Sub Noise Floor Channel Estimation for the Cellular Internet of Things [2,078 bytes]
- (hist) Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) [2,089 bytes]
- (hist) ASIC Design Projects [2,094 bytes]
- (hist) Fault-Tolerant Floating-Point Units (M) [2,097 bytes]
- (hist) Internet of Things SoC Characterization [2,109 bytes]
- (hist) SHAre - An application Specific Instruction Set Processor for SHA-2/3 [2,124 bytes]
- (hist) A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance [2,129 bytes]
- (hist) DC-DC Buck converter in 65nm CMOS [2,131 bytes]
- (hist) A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications [2,135 bytes]
- (hist) Design of a Prototype Chip with Interleaved Memory and Network-on-Chip [2,152 bytes]
- (hist) EvalEDGE: A 2G Cellular Transceiver FMC [2,158 bytes]
- (hist) High Throughput Turbo Decoder Design [2,163 bytes]
- (hist) Machine Learning for extracting Muscle features using Ultrasound [2,167 bytes]
- (hist) Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) [2,176 bytes]
- (hist) Development of an efficient algorithm for quantum transport codes [2,177 bytes]
- (hist) Extension and Evaluation of TinyDMA (1-2S/B/2-3G) [2,186 bytes]
- (hist) Hardware Exploration of Shared-Exponent MiniFloats (M) [2,189 bytes]
- (hist) Low Power Embedded Systems [2,192 bytes]
- (hist) Self Aware Epilepsy Monitoring [2,194 bytes]
- (hist) An Ultra-Low-Power Neuromorphic Spiking Neuron Design [2,197 bytes]
- (hist) An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications [2,200 bytes]
- (hist) LightProbe - Ultracompact Power Supply PCB [2,201 bytes]
- (hist) Taping a Safer Silicon Implementation of Snitch (M/2-3S) [2,217 bytes]
- (hist) LAPACK/BLAS for FPGA [2,219 bytes]
- (hist) Extending the RISCV backend of LLVM to support PULP Extensions [2,219 bytes]
- (hist) Android Software Design [2,224 bytes]
- (hist) Reconfigurability of SHA-3 candidates [2,230 bytes]
- (hist) Flexible Front-End Circuit for Biomedical Data Acquisition [2,232 bytes]
- (hist) Learning Image Decompression with Convolutional Networks [2,236 bytes]
- (hist) Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC [2,237 bytes]
- (hist) Development of a syringe label reader for the neurocritical care unit [2,242 bytes]
- (hist) Machine Learning for extracting Muscle features using Ultrasound 2 [2,257 bytes]
- (hist) Low Power Embedded Systems and Wireless Sensors Networks [2,258 bytes]
- (hist) PREM Runtime Scheduling Policies [2,259 bytes]
- (hist) Triple-Core PULPissimo [2,260 bytes]
- (hist) Energy Neutral Multi Sensors Wearable Device [2,264 bytes]
- (hist) Channel Decoding for TD-HSPA [2,272 bytes]
- (hist) RISC-V base ISA for ultra-low-area cores (2-3G) [2,276 bytes]
- (hist) David J. Mack [2,280 bytes]
- (hist) Real-time eye movement analysis on a tablet computer [2,281 bytes]
- (hist) Baseband Processor Development for 4G IoT [2,283 bytes]
- (hist) Low-power Temperature-insensitive Timer [2,284 bytes]
- (hist) Super Resolution Radar/Imaging at mm-Wave frequencies [2,285 bytes]
- (hist) LightProbe - WIFI extension (PCB) [2,299 bytes]
- (hist) Running Rust on PULP [2,302 bytes]
- (hist) Simulation of 2D artificial cilia metasurface in COMSOL [2,307 bytes]
- (hist) Turbo Decoder Design for High Code Rates [2,309 bytes]
- (hist) Visualizing Functional Microbubbles using Ultrasound Imaging [2,317 bytes]
- (hist) Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials [2,318 bytes]
- (hist) TCNs vs. LSTMs for Embedded Platforms [2,318 bytes]
- (hist) WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing [2,319 bytes]
- (hist) Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) [2,332 bytes]