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  1. (hist) ‎Deconvolution Accelerator for On-Chip Semi-Supervised Learning ‎[0 bytes]
  2. (hist) ‎Neural Processing ‎[0 bytes]
  3. (hist) ‎Near-Memory Training of Neural Networks ‎[0 bytes]
  4. (hist) ‎Biomedical System on Chips ‎[0 bytes]
  5. (hist) ‎Mattia ‎[0 bytes]
  6. (hist) ‎Enabling Standalone Operation ‎[0 bytes]
  7. (hist) ‎Optimal System Duty Cycling ‎[0 bytes]
  8. (hist) ‎Implementation of a Heterogeneous System for Image Processing on an FPGA ‎[0 bytes]
  9. (hist) ‎Palm size chip NMR ‎[0 bytes]
  10. (hist) ‎A Snitch-based Compute Accelerator for HERO ‎[0 bytes]
  11. (hist) ‎(M): A Flexible Peripheral System for High-Performance Systems on Chip ‎[0 bytes]
  12. (hist) ‎IBM Research–Zurich ‎[0 bytes]
  13. (hist) ‎DaCe on Snitch ‎[0 bytes]
  14. (hist) ‎SSR combined with FREP in LLVM/Clang ‎[0 bytes]
  15. (hist) ‎IBM A2O Core ‎[0 bytes]
  16. (hist) ‎IP-Based SoC Generation and Configuration (1-3S) ‎[0 bytes]
  17. (hist) ‎MemPool on HERO ‎[0 bytes]
  18. (hist) ‎ISA extensions in the Snitch Processor for Signal Processing (1M) ‎[0 bytes]
  19. (hist) ‎Integrating Hardware Accelerators into Snitch ‎[0 bytes]
  20. (hist) ‎Prasadar ‎[0 bytes]
  21. (hist) ‎On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks ‎[0 bytes]
  22. (hist) ‎Test project ‎[0 bytes]
  23. (hist) ‎Benchmarking a heterogeneous 217-core MPSoC on HPC applications ‎[0 bytes]
  24. (hist) ‎Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) ‎[0 bytes]
  25. (hist) ‎A Post-Simulation Trace-Based RISC-V GDB Debugging Server ‎[0 bytes]
  26. (hist) ‎Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) ‎[0 bytes]
  27. (hist) ‎Versatile HW SW Digital PHY for inter chip communication ‎[0 bytes]
  28. (hist) ‎Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) ‎[0 bytes]
  29. (hist) ‎Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) ‎[0 bytes]
  30. (hist) ‎Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) ‎[0 bytes]
  31. (hist) ‎Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) ‎[0 bytes]
  32. (hist) ‎Test page ‎[16 bytes]
  33. (hist) ‎A Trustworthy Three-Factor Authentication System ‎[40 bytes]
  34. (hist) ‎Influence of the Initial FilamentGeometry on the Forming Step in CBRAM ‎[75 bytes]
  35. (hist) ‎Theory, Algorithms, and Hardware for Beyond 5G ‎[120 bytes]
  36. (hist) ‎Positioning with Wireless Signals ‎[121 bytes]
  37. (hist) ‎All-Digital In-Memory Processing ‎[121 bytes]
  38. (hist) ‎Real-Time Optimization ‎[121 bytes]
  39. (hist) ‎Audio Signal Processing ‎[123 bytes]
  40. (hist) ‎Simultaneous Sensing and Communication ‎[123 bytes]
  41. (hist) ‎Mixed-Signal Circuit Design ‎[123 bytes]
  42. (hist) ‎Analog IC Design ‎[130 bytes]
  43. (hist) ‎Mixed Signal IC Design ‎[136 bytes]
  44. (hist) ‎AnalogInt ‎[343 bytes]
  45. (hist) ‎Atretter ‎[362 bytes]
  46. (hist) ‎Tbenz ‎[362 bytes]
  47. (hist) ‎Audio ‎[403 bytes]
  48. (hist) ‎Taimir Aguacil ‎[416 bytes]
  49. (hist) ‎Christoph Keller ‎[423 bytes]
  50. (hist) ‎Project Meetings ‎[425 bytes]
  51. (hist) ‎Project Plan ‎[453 bytes]
  52. (hist) ‎Moritz Schneider ‎[459 bytes]
  53. (hist) ‎Software ‎[473 bytes]
  54. (hist) ‎Stefan Lippuner ‎[532 bytes]
  55. (hist) ‎Benjamin Sporrer ‎[567 bytes]
  56. (hist) ‎Philipp Schönle ‎[569 bytes]
  57. (hist) ‎Design Review ‎[577 bytes]
  58. (hist) ‎Nils Wistoff ‎[578 bytes]
  59. (hist) ‎Mauro Salomon ‎[637 bytes]
  60. (hist) ‎Cryptography ‎[645 bytes]
  61. (hist) ‎Libria ‎[646 bytes]
  62. (hist) ‎Karim Badawi ‎[653 bytes]
  63. (hist) ‎Matthias Korb ‎[698 bytes]
  64. (hist) ‎Energy Efficient Circuits and IoT Systems Group ‎[736 bytes]
  65. (hist) ‎EECIS ‎[740 bytes]
  66. (hist) ‎Harald Kröll ‎[764 bytes]
  67. (hist) ‎Pascal Hager ‎[775 bytes]
  68. (hist) ‎Research ‎[789 bytes]
  69. (hist) ‎Ultrasound ‎[797 bytes]
  70. (hist) ‎Federico Villani ‎[834 bytes]
  71. (hist) ‎Coding Guidelines ‎[841 bytes]
  72. (hist) ‎Herschmi ‎[859 bytes]
  73. (hist) ‎Matheus Cavalcante ‎[890 bytes]
  74. (hist) ‎Telecommunications ‎[892 bytes]
  75. (hist) ‎Benjamin Weber ‎[894 bytes]
  76. (hist) ‎Norbert Felber ‎[897 bytes]
  77. (hist) ‎Christoph Leitner ‎[928 bytes]
  78. (hist) ‎Robert Balas ‎[931 bytes]
  79. (hist) ‎GRAND Hardware Implementation ‎[990 bytes]
  80. (hist) ‎FPGA ‎[1,020 bytes]
  81. (hist) ‎Matteo Perotti ‎[1,028 bytes]
  82. (hist) ‎Andreas Kurth ‎[1,029 bytes]
  83. (hist) ‎Fabian Schuiki ‎[1,031 bytes]
  84. (hist) ‎Stefan Mach ‎[1,044 bytes]
  85. (hist) ‎Eye tracking ‎[1,058 bytes]
  86. (hist) ‎Integrated Devices, Electronics, And Systems ‎[1,058 bytes]
  87. (hist) ‎Frank K. Gürkaynak ‎[1,072 bytes]
  88. (hist) ‎Low-Power Time Synchronization for IoT Applications ‎[1,085 bytes]
  89. (hist) ‎Physical Layer Implementation of HSPA+ 4G Mobile Transceiver ‎[1,088 bytes]
  90. (hist) ‎Guillaume Mocquard ‎[1,117 bytes]
  91. (hist) ‎Final Presentation ‎[1,130 bytes]
  92. (hist) ‎Channel Estimation for 3GPP TD-SCDMA ‎[1,144 bytes]
  93. (hist) ‎Synchronization and Power Control Concepts for 3GPP TD-SCDMA ‎[1,145 bytes]
  94. (hist) ‎Michael Muehlberghuber ‎[1,160 bytes]
  95. (hist) ‎An FPGA-Based Testbed for 3G Mobile Communications Receivers ‎[1,168 bytes]
  96. (hist) ‎FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications ‎[1,194 bytes]
  97. (hist) ‎Michael Rogenmoser ‎[1,211 bytes]
  98. (hist) ‎Interference Cancellation for EC-GSM-IoT ‎[1,281 bytes]
  99. (hist) ‎Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M) ‎[1,284 bytes]
  100. (hist) ‎ASIC ‎[1,286 bytes]
  101. (hist) ‎PREM on PULP ‎[1,304 bytes]
  102. (hist) ‎Configurable Ultra Low Power LDO ‎[1,306 bytes]
  103. (hist) ‎Exploring Algorithms for Early Seizure Detection ‎[1,329 bytes]
  104. (hist) ‎SW/HW Predictability and Security ‎[1,333 bytes]
  105. (hist) ‎Modeling High Bandwidth Memory for Rapid Design Space Exploration (1-3S/B) ‎[1,378 bytes]
  106. (hist) ‎Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B) ‎[1,408 bytes]
  107. (hist) ‎Design of low mismatch DAC used for VAD ‎[1,409 bytes]
  108. (hist) ‎Scan Chain Fault Injection in a PULP SoC (1S) ‎[1,421 bytes]
  109. (hist) ‎Receiver design for the DigRF 4G high speed serial link ‎[1,431 bytes]
  110. (hist) ‎Beat Cadence ‎[1,442 bytes]
  111. (hist) ‎Precise Ultra-low-power Timer ‎[1,446 bytes]
  112. (hist) ‎Digital Audio Processor for Cellular Applications ‎[1,448 bytes]
  113. (hist) ‎Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) ‎[1,466 bytes]
  114. (hist) ‎Multiuser Equalization and Detection for 3GPP TD-SCDMA ‎[1,484 bytes]
  115. (hist) ‎Creating A Boundry Scan Generator (1-3S/B/2-3G) ‎[1,488 bytes]
  116. (hist) ‎Design of a D-Band Variable Gain Amplifier for 6G Communication ‎[1,522 bytes]
  117. (hist) ‎Positioning for the cellular Internet of Things ‎[1,525 bytes]
  118. (hist) ‎ASIC Design of a Gaussian Message Passing Processor ‎[1,526 bytes]
  119. (hist) ‎Pirmin Vogel ‎[1,528 bytes]
  120. (hist) ‎Novel Metastability Mitigation Technique ‎[1,561 bytes]
  121. (hist) ‎High resolution, low power Sigma Delta ADC ‎[1,568 bytes]
  122. (hist) ‎Marco Bertuletti ‎[1,571 bytes]
  123. (hist) ‎Hardware Accelerator Integration into Embedded Linux ‎[1,578 bytes]
  124. (hist) ‎LightProbe - CNN-Based-Image-Reconstruction ‎[1,582 bytes]
  125. (hist) ‎Hardware Support for IDE in Multicore Environment ‎[1,591 bytes]
  126. (hist) ‎Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B) ‎[1,597 bytes]
  127. (hist) ‎Ultrasound signal processing acceleration with CUDA ‎[1,600 bytes]
  128. (hist) ‎Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B) ‎[1,645 bytes]
  129. (hist) ‎Synchronisation and Cyclic Prefix Handling For LTE Testbed ‎[1,649 bytes]
  130. (hist) ‎Audio Video Preprocessing In Parallel Ultra Low Power Platform ‎[1,650 bytes]
  131. (hist) ‎Fast Wakeup From Deep Sleep State ‎[1,665 bytes]
  132. (hist) ‎Fault Tolerance ‎[1,665 bytes]
  133. (hist) ‎EvaLTE: A 2G/3G/4G Cellular Transceiver FMC ‎[1,679 bytes]
  134. (hist) ‎Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B) ‎[1,705 bytes]
  135. (hist) ‎GSM Voice Capacity Evolution - VAMOS ‎[1,707 bytes]
  136. (hist) ‎Next-Gen Ultrasound Imaging Systems (Industry Student Projects & PhD Opportunity) ‎[1,722 bytes]
  137. (hist) ‎Design and Implementation of a multi-mode multi-master I2C peripheral ‎[1,729 bytes]
  138. (hist) ‎Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B) ‎[1,729 bytes]
  139. (hist) ‎System Analysis and VLSI Design of NB-IoT Baseband Processing ‎[1,736 bytes]
  140. (hist) ‎Toward Superposition of Brain-Computer Interface Models ‎[1,758 bytes]
  141. (hist) ‎State-Saving @ NXP ‎[1,767 bytes]
  142. (hist) ‎Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G) ‎[1,776 bytes]
  143. (hist) ‎Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B) ‎[1,794 bytes]
  144. (hist) ‎Power Saver Mode for Cellular Internet of Things Receivers ‎[1,795 bytes]
  145. (hist) ‎Bluetooth Low Energy receiver in 65nm CMOS ‎[1,795 bytes]
  146. (hist) ‎Adding Linux Support to our DMA Engine (1-2S/B) ‎[1,795 bytes]
  147. (hist) ‎LTE-Advanced RF Front-end Design in 28nm CMOS Technology ‎[1,811 bytes]
  148. (hist) ‎5G Cellular RF Front-end Design in 22nm CMOS Technology ‎[1,818 bytes]
  149. (hist) ‎AXI-based Network on Chip (NoC) system ‎[1,825 bytes]
  150. (hist) ‎Energy Efficient Serial Link ‎[1,833 bytes]
  151. (hist) ‎LightProbe - 192cha Multiplexer Stage (Rigid-Flex-PCB Project) ‎[1,841 bytes]
  152. (hist) ‎Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets ‎[1,852 bytes]
  153. (hist) ‎Open Source Baseband Firmware for 2G Cellular Networks ‎[1,858 bytes]
  154. (hist) ‎Interference Cancellation for the cellular Internet of Things ‎[1,860 bytes]
  155. (hist) ‎Bluetooth Low Energy network with optimized data throughput ‎[1,860 bytes]
  156. (hist) ‎Ultrasound Low power WiFi with IMX7 ‎[1,861 bytes]
  157. (hist) ‎Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets ‎[1,863 bytes]
  158. (hist) ‎Fast and Accurate Multiclass Inference for Brain–Computer Interfaces ‎[1,865 bytes]
  159. (hist) ‎Low-Dropout Regulators for Magnetic Resonance Imaging ‎[1,867 bytes]
  160. (hist) ‎Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M) ‎[1,878 bytes]
  161. (hist) ‎Wiederverwendung (reuse) ganzer Funktionsblöcke beim VLSI-Entwurf ‎[1,896 bytes]
  162. (hist) ‎Implementation of a Coherent Application-Class Multicore System (1-2S) ‎[1,897 bytes]
  163. (hist) ‎Multi-Band Receiver Design for LTE Mobile Communication ‎[1,907 bytes]
  164. (hist) ‎LightProbe ‎[1,907 bytes]
  165. (hist) ‎Near-Optimal Reduced-Complexity Sequence Detectors for TD-HSPA ‎[1,914 bytes]
  166. (hist) ‎Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) ‎[1,929 bytes]
  167. (hist) ‎Praxisgerechte Berechnung von Switching Noise in VLSI-Schaltungen ‎[1,931 bytes]
  168. (hist) ‎Enabling Standalone Operation for a Mobile Health Platform ‎[1,934 bytes]
  169. (hist) ‎Soft-Output Viterbi Equalizer as part of Evolved EDGE baseband ASIC ‎[1,946 bytes]
  170. (hist) ‎GUI-developement for an action-cam-based eye tracking device ‎[1,949 bytes]
  171. (hist) ‎High Performance Cellular Receivers in Very Advanced CMOS ‎[1,952 bytes]
  172. (hist) ‎Make Cellular Internet of Things Receivers Smart ‎[1,954 bytes]
  173. (hist) ‎Towards Formal Verification of the iDMA Engine (1-3S/B) ‎[1,954 bytes]
  174. (hist) ‎Non-binary LDPC Decoder for Deep-Space Optical Communications ‎[1,958 bytes]
  175. (hist) ‎Jammer-Resilient Synchronization for Wireless Communications ‎[1,962 bytes]
  176. (hist) ‎Wireless Biomedical Signal Acquisition Device ‎[1,982 bytes]
  177. (hist) ‎3D Ultrasound Bubble Tracking ‎[1,982 bytes]
  178. (hist) ‎RazorEDGE: An Evolved EDGE DBB ASIC ‎[1,995 bytes]
  179. (hist) ‎Implementation of a Cache Reliability Mechanism (1S/M) ‎[1,996 bytes]
  180. (hist) ‎ASIC Design of a Sigma Point Processor ‎[1,998 bytes]
  181. (hist) ‎Beat DigRF ‎[2,000 bytes]
  182. (hist) ‎Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening ‎[2,001 bytes]
  183. (hist) ‎Energy Efficient AXI Interface to Serial Link Physical Layer ‎[2,020 bytes]
  184. (hist) ‎High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS ‎[2,024 bytes]
  185. (hist) ‎Signal to Noise Ratio Estimation for 3G standards ‎[2,025 bytes]
  186. (hist) ‎Channel Estimation for TD-HSPA ‎[2,028 bytes]
  187. (hist) ‎Event-Driven Computing ‎[2,043 bytes]
  188. (hist) ‎Interference Cancellation for Evolved EDGE on the RazorEDGE baseband ASIC ‎[2,044 bytes]
  189. (hist) ‎Acceleration and Transprecision ‎[2,054 bytes]
  190. (hist) ‎Implementation of an AES Hardware Processing Engine (B/S) ‎[2,064 bytes]
  191. (hist) ‎Analog building blocks for mmWave manipulation ‎[2,064 bytes]
  192. (hist) ‎Intelligent Power Management Unit (iPMU) ‎[2,067 bytes]
  193. (hist) ‎Compression of Ultrasound data on FPGA ‎[2,067 bytes]
  194. (hist) ‎Predictable Execution ‎[2,068 bytes]
  195. (hist) ‎Machine Learning on Ultrasound Images ‎[2,071 bytes]
  196. (hist) ‎Design of a Digital Audio Module for Ultra-Low Power Cellular Applications ‎[2,072 bytes]
  197. (hist) ‎Improving Resiliency of Hyperdimensional Computing ‎[2,073 bytes]
  198. (hist) ‎Audio DAC Conversion Jitter Measurement System ‎[2,075 bytes]
  199. (hist) ‎Sub Noise Floor Channel Estimation for the Cellular Internet of Things ‎[2,078 bytes]
  200. (hist) ‎Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G) ‎[2,089 bytes]
  201. (hist) ‎ASIC Design Projects ‎[2,094 bytes]
  202. (hist) ‎Fault-Tolerant Floating-Point Units (M) ‎[2,097 bytes]
  203. (hist) ‎Internet of Things SoC Characterization ‎[2,109 bytes]
  204. (hist) ‎SHAre - An application Specific Instruction Set Processor for SHA-2/3 ‎[2,124 bytes]
  205. (hist) ‎A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance ‎[2,129 bytes]
  206. (hist) ‎DC-DC Buck converter in 65nm CMOS ‎[2,131 bytes]
  207. (hist) ‎A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications ‎[2,135 bytes]
  208. (hist) ‎Design of a Prototype Chip with Interleaved Memory and Network-on-Chip ‎[2,152 bytes]
  209. (hist) ‎EvalEDGE: A 2G Cellular Transceiver FMC ‎[2,158 bytes]
  210. (hist) ‎High Throughput Turbo Decoder Design ‎[2,163 bytes]
  211. (hist) ‎Machine Learning for extracting Muscle features using Ultrasound ‎[2,167 bytes]
  212. (hist) ‎Towards a High-performance Open-source Verification Suite for AXI-based Systems (M/1-3S/B) ‎[2,176 bytes]
  213. (hist) ‎Development of an efficient algorithm for quantum transport codes ‎[2,177 bytes]
  214. (hist) ‎Extension and Evaluation of TinyDMA (1-2S/B/2-3G) ‎[2,186 bytes]
  215. (hist) ‎Hardware Exploration of Shared-Exponent MiniFloats (M) ‎[2,189 bytes]
  216. (hist) ‎Low Power Embedded Systems ‎[2,192 bytes]
  217. (hist) ‎Self Aware Epilepsy Monitoring ‎[2,194 bytes]
  218. (hist) ‎An Ultra-Low-Power Neuromorphic Spiking Neuron Design ‎[2,197 bytes]
  219. (hist) ‎An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications ‎[2,200 bytes]
  220. (hist) ‎LightProbe - Ultracompact Power Supply PCB ‎[2,201 bytes]
  221. (hist) ‎Taping a Safer Silicon Implementation of Snitch (M/2-3S) ‎[2,217 bytes]
  222. (hist) ‎LAPACK/BLAS for FPGA ‎[2,219 bytes]
  223. (hist) ‎Extending the RISCV backend of LLVM to support PULP Extensions ‎[2,219 bytes]
  224. (hist) ‎Android Software Design ‎[2,224 bytes]
  225. (hist) ‎Reconfigurability of SHA-3 candidates ‎[2,230 bytes]
  226. (hist) ‎Flexible Front-End Circuit for Biomedical Data Acquisition ‎[2,232 bytes]
  227. (hist) ‎Learning Image Decompression with Convolutional Networks ‎[2,236 bytes]
  228. (hist) ‎Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC ‎[2,237 bytes]
  229. (hist) ‎Development of a syringe label reader for the neurocritical care unit ‎[2,242 bytes]
  230. (hist) ‎Machine Learning for extracting Muscle features using Ultrasound 2 ‎[2,257 bytes]
  231. (hist) ‎Low Power Embedded Systems and Wireless Sensors Networks ‎[2,258 bytes]
  232. (hist) ‎PREM Runtime Scheduling Policies ‎[2,259 bytes]
  233. (hist) ‎Triple-Core PULPissimo ‎[2,260 bytes]
  234. (hist) ‎Energy Neutral Multi Sensors Wearable Device ‎[2,264 bytes]
  235. (hist) ‎Channel Decoding for TD-HSPA ‎[2,272 bytes]
  236. (hist) ‎RISC-V base ISA for ultra-low-area cores (2-3G) ‎[2,276 bytes]
  237. (hist) ‎David J. Mack ‎[2,280 bytes]
  238. (hist) ‎Real-time eye movement analysis on a tablet computer ‎[2,281 bytes]
  239. (hist) ‎Baseband Processor Development for 4G IoT ‎[2,283 bytes]
  240. (hist) ‎Low-power Temperature-insensitive Timer ‎[2,284 bytes]
  241. (hist) ‎Super Resolution Radar/Imaging at mm-Wave frequencies ‎[2,285 bytes]
  242. (hist) ‎LightProbe - WIFI extension (PCB) ‎[2,299 bytes]
  243. (hist) ‎Running Rust on PULP ‎[2,302 bytes]
  244. (hist) ‎Simulation of 2D artificial cilia metasurface in COMSOL ‎[2,307 bytes]
  245. (hist) ‎Turbo Decoder Design for High Code Rates ‎[2,309 bytes]
  246. (hist) ‎Visualizing Functional Microbubbles using Ultrasound Imaging ‎[2,317 bytes]
  247. (hist) ‎Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials ‎[2,318 bytes]
  248. (hist) ‎TCNs vs. LSTMs for Embedded Platforms ‎[2,318 bytes]
  249. (hist) ‎WCDMA/HSPA+ Synchronization System Design, Implementation, and Testing ‎[2,319 bytes]
  250. (hist) ‎Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B) ‎[2,332 bytes]

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