Short pages

Showing below up to 50 results in range #1 to #50.

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1. (hist) ‎Deconvolution Accelerator for On-Chip Semi-Supervised Learning ‎[0 bytes]
2. (hist) ‎Neural Processing ‎[0 bytes]
3. (hist) ‎Near-Memory Training of Neural Networks ‎[0 bytes]
4. (hist) ‎Biomedical System on Chips ‎[0 bytes]
5. (hist) ‎Mattia ‎[0 bytes]
6. (hist) ‎Enabling Standalone Operation ‎[0 bytes]
7. (hist) ‎Optimal System Duty Cycling ‎[0 bytes]
8. (hist) ‎Implementation of a Heterogeneous System for Image Processing on an FPGA ‎[0 bytes]
9. (hist) ‎Palm size chip NMR ‎[0 bytes]
10. (hist) ‎A Snitch-based Compute Accelerator for HERO ‎[0 bytes]
11. (hist) ‎(M): A Flexible Peripheral System for High-Performance Systems on Chip ‎[0 bytes]
12. (hist) ‎IBM Research–Zurich ‎[0 bytes]
13. (hist) ‎DaCe on Snitch ‎[0 bytes]
14. (hist) ‎SSR combined with FREP in LLVM/Clang ‎[0 bytes]
15. (hist) ‎IBM A2O Core ‎[0 bytes]
16. (hist) ‎IP-Based SoC Generation and Configuration (1-3S) ‎[0 bytes]
17. (hist) ‎MemPool on HERO ‎[0 bytes]
18. (hist) ‎ISA extensions in the Snitch Processor for Signal Processing (1M) ‎[0 bytes]
19. (hist) ‎Integrating Hardware Accelerators into Snitch ‎[0 bytes]
20. (hist) ‎Prasadar ‎[0 bytes]
21. (hist) ‎On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks ‎[0 bytes]
22. (hist) ‎Test project ‎[0 bytes]
23. (hist) ‎Benchmarking a heterogeneous 217-core MPSoC on HPC applications ‎[0 bytes]
24. (hist) ‎Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) ‎[0 bytes]
25. (hist) ‎A Post-Simulation Trace-Based RISC-V GDB Debugging Server ‎[0 bytes]
26. (hist) ‎Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) ‎[0 bytes]
27. (hist) ‎Versatile HW SW Digital PHY for inter chip communication ‎[0 bytes]
28. (hist) ‎Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) ‎[0 bytes]
29. (hist) ‎Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) ‎[0 bytes]
30. (hist) ‎Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) ‎[0 bytes]
31. (hist) ‎Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) ‎[0 bytes]
32. (hist) ‎Test page ‎[16 bytes]
33. (hist) ‎A Trustworthy Three-Factor Authentication System ‎[40 bytes]
34. (hist) ‎Influence of the Initial FilamentGeometry on the Forming Step in CBRAM ‎[75 bytes]
35. (hist) ‎Theory, Algorithms, and Hardware for Beyond 5G ‎[120 bytes]
36. (hist) ‎Positioning with Wireless Signals ‎[121 bytes]
37. (hist) ‎All-Digital In-Memory Processing ‎[121 bytes]
38. (hist) ‎Real-Time Optimization ‎[121 bytes]
39. (hist) ‎Audio Signal Processing ‎[123 bytes]
40. (hist) ‎Simultaneous Sensing and Communication ‎[123 bytes]
41. (hist) ‎Mixed-Signal Circuit Design ‎[123 bytes]
42. (hist) ‎Analog IC Design ‎[130 bytes]
43. (hist) ‎Mixed Signal IC Design ‎[136 bytes]
44. (hist) ‎AnalogInt ‎[343 bytes]
45. (hist) ‎Atretter ‎[362 bytes]
46. (hist) ‎Tbenz ‎[362 bytes]
47. (hist) ‎Audio ‎[403 bytes]
48. (hist) ‎Taimir Aguacil ‎[416 bytes]
49. (hist) ‎Christoph Keller ‎[423 bytes]
50. (hist) ‎Project Meetings ‎[425 bytes]

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