Short pages
From iis-projects
Showing below up to 50 results in range #1 to #50.
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- (hist) Deconvolution Accelerator for On-Chip Semi-Supervised Learning [0 bytes]
- (hist) Neural Processing [0 bytes]
- (hist) Near-Memory Training of Neural Networks [0 bytes]
- (hist) Biomedical System on Chips [0 bytes]
- (hist) Mattia [0 bytes]
- (hist) Enabling Standalone Operation [0 bytes]
- (hist) Optimal System Duty Cycling [0 bytes]
- (hist) Implementation of a Heterogeneous System for Image Processing on an FPGA [0 bytes]
- (hist) Palm size chip NMR [0 bytes]
- (hist) A Snitch-based Compute Accelerator for HERO [0 bytes]
- (hist) (M): A Flexible Peripheral System for High-Performance Systems on Chip [0 bytes]
- (hist) IBM Research–Zurich [0 bytes]
- (hist) DaCe on Snitch [0 bytes]
- (hist) SSR combined with FREP in LLVM/Clang [0 bytes]
- (hist) IBM A2O Core [0 bytes]
- (hist) IP-Based SoC Generation and Configuration (1-3S) [0 bytes]
- (hist) MemPool on HERO [0 bytes]
- (hist) ISA extensions in the Snitch Processor for Signal Processing (1M) [0 bytes]
- (hist) Integrating Hardware Accelerators into Snitch [0 bytes]
- (hist) Prasadar [0 bytes]
- (hist) On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks [0 bytes]
- (hist) Test project [0 bytes]
- (hist) Benchmarking a heterogeneous 217-core MPSoC on HPC applications [0 bytes]
- (hist) Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)) [0 bytes]
- (hist) A Post-Simulation Trace-Based RISC-V GDB Debugging Server [0 bytes]
- (hist) Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M) [0 bytes]
- (hist) Versatile HW SW Digital PHY for inter chip communication [0 bytes]
- (hist) Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S) [0 bytes]
- (hist) Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S) [0 bytes]
- (hist) Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B) [0 bytes]
- (hist) Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S) [0 bytes]
- (hist) Test page [16 bytes]
- (hist) A Trustworthy Three-Factor Authentication System [40 bytes]
- (hist) Influence of the Initial FilamentGeometry on the Forming Step in CBRAM [75 bytes]
- (hist) Theory, Algorithms, and Hardware for Beyond 5G [120 bytes]
- (hist) Positioning with Wireless Signals [121 bytes]
- (hist) All-Digital In-Memory Processing [121 bytes]
- (hist) Real-Time Optimization [121 bytes]
- (hist) Audio Signal Processing [123 bytes]
- (hist) Simultaneous Sensing and Communication [123 bytes]
- (hist) Mixed-Signal Circuit Design [123 bytes]
- (hist) Analog IC Design [130 bytes]
- (hist) Mixed Signal IC Design [136 bytes]
- (hist) AnalogInt [343 bytes]
- (hist) Atretter [362 bytes]
- (hist) Tbenz [362 bytes]
- (hist) Audio [403 bytes]
- (hist) Taimir Aguacil [416 bytes]
- (hist) Christoph Keller [423 bytes]
- (hist) Project Meetings [425 bytes]