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- GRAND Hardware Implementation
- HW/SW Safety and Security
- Hardware Acceleration
- Heterogeneous SoCs
- High Performance SoCs
- Hyperdimensional Computing
- IBM A2O Core
- IBM Research–Zurich
- IP-Based SoC Generation and Configuration (1-3S)
- ISA extensions in the Snitch Processor for Signal Processing (1M)
- Implementation of a 2-D model for Li-ion batteries
- Implementation of a Heterogeneous System for Image Processing on an FPGA
- Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
- Influence of the Initial Filament Geometry on the Forming Step in CBRAM
- Integrated Devices, Electronics, And Systems
- Integrated Information Processing
- Integrated silicon photonic structures
- Integrating Hardware Accelerators into Snitch
- Investigation of the source starvation effect in III-V MOSFET
- Low-Power Time Synchronization for IoT Applications
- Low-power chip-to-chip communication network
- Low Power Embedded Systems
- Low Power Embedded Systems and Wireless Sensors Networks
- Main Page
- Marco Bertuletti
- Matteo Perotti
- Mattia
- MemPool on HERO
- Michael Rogenmoser
- Mixed-Signal Circuit Design
- Mixed Signal IC Design
- NAND Flash Open Research Platform
- Near-Memory Training of Neural Networks
- Neural Processing
- NextGenChannelDec
- Nils Wistoff
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
- On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
- Optimal System Duty Cycling
- Optimal System Duty Cycling for a Mobile Health Platform
- Palm size chip NMR
- Positioning with Wireless Signals
- Prasadar
- Predictable Execution
- Real-Time Embedded Systems
- Real-Time Optimization
- Research
- Robert Balas
- SSR combined with FREP in LLVM/Clang
- SW/HW Predictability and Security