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Showing below up to 121 results in range #1 to #121.

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  1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
  2. ASIC
  3. ASIC Design Projects
  4. A Post-Simulation Trace-Based RISC-V GDB Debugging Server
  5. A Snitch-based Compute Accelerator for HERO
  6. Ab-initio Simulation of Strained Thermoelectric Materials
  7. Acceleration and Transprecision
  8. All-Digital In-Memory Processing
  9. Analog
  10. AnalogInt
  11. Analog IC Design
  12. Android Software Design
  13. Atretter
  14. Audio
  15. Audio Signal Processing
  16. Benchmarking a heterogeneous 217-core MPSoC on HPC applications
  17. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
  18. Biomedical System on Chips
  19. Biomedical Systems on Chip
  20. Brunn test
  21. Circuits and Systems for Nanoelectrode Array Biosensors
  22. Completed
  23. Computation of Phonon Bandstructure in III-V Nanostructures
  24. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
  25. Cryptography
  26. DaCe on Snitch
  27. Deconvolution Accelerator for On-Chip Semi-Supervised Learning
  28. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
  29. Deep Learning Projects
  30. Design and Implementation of a multi-mode multi-master I2C peripheral
  31. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
  32. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
  33. Design study of tunneling transistors based on a core/shell nanowire structures
  34. Development of a fingertip blood pressure sensor
  35. Digital Medical Ultrasound Imaging
  36. EECIS
  37. Elliptic Curve Accelerator for zkSNARKs
  38. Embedded Artificial Intelligence:Systems And Applications
  39. Embedded Systems and autonomous UAVs
  40. Enabling Standalone Operation
  41. Enabling Standalone Operation for a Mobile Health Platform
  42. Energy Efficient Circuits and IoT Systems Group
  43. Energy Efficient SoCs
  44. Event-Driven Computing
  45. Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  46. FPGA
  47. Fault Tolerance
  48. Finite Element Simulations of Transistors for Quantum Computing
  49. Flexible Electronic Systems and Embedded Epidermal Devices
  50. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  51. GRAND Hardware Implementation
  52. HW/SW Safety and Security
  53. Hardware Acceleration
  54. Heterogeneous SoCs
  55. High Performance SoCs
  56. Hyperdimensional Computing
  57. IBM A2O Core
  58. IBM Research–Zurich
  59. IP-Based SoC Generation and Configuration (1-3S)
  60. ISA extensions in the Snitch Processor for Signal Processing (1M)
  61. Implementation of a 2-D model for Li-ion batteries
  62. Implementation of a Heterogeneous System for Image Processing on an FPGA
  63. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
  64. Influence of the Initial Filament Geometry on the Forming Step in CBRAM
  65. Integrated Devices, Electronics, And Systems
  66. Integrated Information Processing
  67. Integrated silicon photonic structures
  68. Integrating Hardware Accelerators into Snitch
  69. Investigation of the source starvation effect in III-V MOSFET
  70. Low-Power Time Synchronization for IoT Applications
  71. Low-power chip-to-chip communication network
  72. Low Power Embedded Systems
  73. Low Power Embedded Systems and Wireless Sensors Networks
  74. Main Page
  75. Marco Bertuletti
  76. Matteo Perotti
  77. Mattia
  78. MemPool on HERO
  79. Michael Rogenmoser
  80. Mixed-Signal Circuit Design
  81. Mixed Signal IC Design
  82. NAND Flash Open Research Platform
  83. Near-Memory Training of Neural Networks
  84. Neural Processing
  85. NextGenChannelDec
  86. Nils Wistoff
  87. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks
  88. On-Device Training Sparse Sub-Tensor Update Scheme Optimization for CNN-based tasks (SA or MA)
  89. Optimal System Duty Cycling
  90. Optimal System Duty Cycling for a Mobile Health Platform
  91. Palm size chip NMR
  92. Positioning with Wireless Signals
  93. Prasadar
  94. Predictable Execution
  95. Real-Time Embedded Systems
  96. Real-Time Optimization
  97. Research
  98. Robert Balas
  99. SSR combined with FREP in LLVM/Clang
  100. SW/HW Predictability and Security
  101. Simulation of Li-ion batteries and comparison with experimental data
  102. Simulation of Negative Capacitance Ferroelectric Transistor
  103. Simultaneous Sensing and Communication
  104. Skin coupling media characterization for fitnesstracker applications (1 B/S)
  105. Smart Goggles for Visual In-Action Feedback in Ski Jumping (1 B/S)
  106. Smart Googles for Visual In-Action Feedback in Ski Jumping (1 B/S)
  107. Software
  108. Students' Interanational Competitions: F1(AMZ), Swissloop, Educational Rockets
  109. Students' International Competitions: F1(AMZ), Swissloop, Educational Rockets
  110. SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
  111. Tbenz
  112. Telecommunications
  113. Template
  114. Test page
  115. Test project
  116. Theory, Algorithms, and Hardware for Beyond 5G
  117. Ultrasound
  118. Versatile HW SW Digital PHY for inter chip communication
  119. Wearables for Sports and Fitness Tracking
  120. Wearables for Sports and Life Enhancement
  121. Weekly Reports

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