Pages that link to "User:Paulsc"
From iis-projects
The following pages link to User:Paulsc:
View (previous 500 | next 500) (20 | 50 | 100 | 250 | 500)- High Performance SoCs (← links)
- A Flexible Peripheral System for High-Performance Systems on Chip (M) (← links)
- A Snitch-based Compute Accelerator for HERO (M/1-2S) (← links)
- SSR combined with FREP in LLVM/Clang (M/1-3S) (← links)
- DaCe on Snitch (M/1-3S) (← links)
- Software-Defined Paging in the Snitch Cluster (2-3S) (← links)
- Category:Paulsc (redirect page) (← links)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G) (← links)
- Hardware Acceleration (← links)
- IP-Based SoC Generation and Configuration (1-3S/B) (← links)
- RISC-V base ISA for ultra-low-area cores (2-3G) (← links)
- Quest for the smallest Turing-complete core (2-3G) (← links)
- Snitch meets iCE40 (1-2S/B) (← links)
- Evaluating memory access pattern specializations in OoO, server-grade cores (M) (← links)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S) (← links)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B) (← links)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G) (← links)
- LLVM and DaCe for Snitch (1-2S) (← links)
- Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S) (← links)
- Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs (← links)
- Augmenting Our IPs with AXI Stream Extensions (M/1-2S) (← links)
- A Unified Compute Kernel Library for Snitch (1-2S) (← links)
- Implementing DSP Instructions in Banshee (1S) (← links)
- Streaming Integer Extensions for Snitch (M/1-2S) (← links)
- Extension and Evaluation of TinyDMA (1-2S/B/2-3G) (← links)
- Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S) (← links)
- Towards Formal Verification of the iDMA Engine (1-3S/B) (← links)
- An Efficient Compiler Backend for Snitch (1S/B) (← links)
- Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B) (← links)
- Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B) (← links)
- A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S) (← links)
- Taping a Safer Silicon Implementation of Snitch (M/2-3S) (← links)
- Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S) (← links)
- A RISC-V ISA Extension for Scalar Chaining in Snitch (M) (← links)