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  1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
  2. 3D Matrix Multiplication Unit for ITA (1S)
  3. 3D Turbo Decoder ASIC Realization
  4. 3D Ultrasound Bubble Tracking
  5. 4th Generation Synchronization
  6. 5G Cellular RF Front-end Design in 22nm CMOS Technology
  7. AMZ Driverless Competition Embedded Systems Projects
  8. ASIC
  9. ASIC Design Projects
  10. ASIC Design of a Gaussian Message Passing Processor
  11. ASIC Design of a Sigma Point Processor
  12. ASIC Development of 5G-NR LDPC Decoder
  13. ASIC Implementation of High-Throughput Next Generation Turbo Decoders
  14. ASIC Implementation of Jammer Mitigation
  15. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
  16. ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
  17. ASIC implementation of an interpolation-based wideband massive MIMO detector
  18. ASR-Waveformer
  19. AXI-based Network on Chip (NoC) system
  20. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
  21. A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
  22. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
  23. A Flexible Peripheral System for High-Performance Systems on Chip (M)
  24. A Multiview Synthesis Core in 65 nm CMOS
  25. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
  26. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
  27. A Post-Simulation Trace-Based RISC-V GDB Debugging Server
  28. A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
  29. A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
  30. A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
  31. A Recurrent Neural Network Speech Recognition Chip
  32. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  33. A Snitch-based Compute Accelerator for HERO
  34. A Snitch-based Compute Accelerator for HERO (M/1-2S)
  35. A Trustworthy Three-Factor Authentication System
  36. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  37. A Unified Compute Kernel Library for Snitch (1-2S)
  38. A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
  39. A Wearable System To Control Phone And Electronic Device Without Hands
  40. A Wearable System for long term monitoring of human physiological parameters with E skin sensors
  41. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  42. A Wireless Sensor Network for HPC monitoring
  43. A Wireless Sensor Network for a Smart Building Monitor and Control
  44. A Wireless Sensor Network for a Smart LED Lighting control
  45. A computational memory unit using phase-change memory devices
  46. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
  47. A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
  48. Ab-initio Simulation of Strained Thermoelectric Materials
  49. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  50. Accelerating Matrix Multiplication on a 216-core MPSoC (1M)

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