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Showing below up to 500 results in range #1 to #500.

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  1. (M): A Flexible Peripheral System for High-Performance Systems on Chip
  2. 3D Matrix Multiplication Unit for ITA (1S)
  3. 3D Turbo Decoder ASIC Realization
  4. 3D Ultrasound Bubble Tracking
  5. 4th Generation Synchronization
  6. 5G Cellular RF Front-end Design in 22nm CMOS Technology
  7. AMZ Driverless Competition Embedded Systems Projects
  8. ASIC
  9. ASIC Design Projects
  10. ASIC Design of a Gaussian Message Passing Processor
  11. ASIC Design of a Sigma Point Processor
  12. ASIC Development of 5G-NR LDPC Decoder
  13. ASIC Implementation of High-Throughput Next Generation Turbo Decoders
  14. ASIC Implementation of Jammer Mitigation
  15. ASIC Implementation of a Low-Power mmWave Massive MIMO Equalizer with a Custom Number Format
  16. ASIC implementation of a beamspace massive MIMO-OFDM detector for 5G/6G
  17. ASIC implementation of an interpolation-based wideband massive MIMO detector
  18. ASR-Waveformer
  19. AXI-based Network on Chip (NoC) system
  20. A Demonstrator of Non-Synchronized Hyperdimensional Body Area Networks
  21. A FPGA-based data streaming system that enables real-time monitoring of cell culture and neuroactivities
  22. A Flexible FPGA-Based Peripheral Platform Extending Linux-Capable Systems on Chip (1-3S/B)
  23. A Flexible Peripheral System for High-Performance Systems on Chip (M)
  24. A Multiview Synthesis Core in 65 nm CMOS
  25. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance
  26. A Novel Execution Scheme for Ultra-tiny CNNs Aboard Nano-UAVs
  27. A Post-Simulation Trace-Based RISC-V GDB Debugging Server
  28. A RISC-V ISA Extension for Pseudo Dual-Issue Monte Carlo in Snitch (1M/2S)
  29. A RISC-V ISA Extension for Scalar Chaining in Snitch (M)
  30. A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
  31. A Recurrent Neural Network Speech Recognition Chip
  32. A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
  33. A Snitch-based Compute Accelerator for HERO
  34. A Snitch-based Compute Accelerator for HERO (M/1-2S)
  35. A Trustworthy Three-Factor Authentication System
  36. A Unified-Multiplier Based Hardware Architecture for Elliptic Curve Cryptography
  37. A Unified Compute Kernel Library for Snitch (1-2S)
  38. A Waypoint-based Navigation System for Nano-Size UAVs in GPS-denied Environments
  39. A Wearable System To Control Phone And Electronic Device Without Hands
  40. A Wearable System for long term monitoring of human physiological parameters with E skin sensors
  41. A Wearable Wireless Kidney Function Monitoring System For BioMedical Applications
  42. A Wireless Sensor Network for HPC monitoring
  43. A Wireless Sensor Network for a Smart Building Monitor and Control
  44. A Wireless Sensor Network for a Smart LED Lighting control
  45. A computational memory unit using phase-change memory devices
  46. A mmWave Voltage-Controlled-Oscillator (VCO) for beyond 5G applications
  47. A reduction-capable AXI XBAR for fast M-to-1 communication (1M)
  48. Ab-initio Simulation of Strained Thermoelectric Materials
  49. Accelerating Applications Relying on Matrix-Vector-Product-Like Operations
  50. Accelerating Matrix Multiplication on a 216-core MPSoC (1M)
  51. Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
  52. Acceleration and Transprecision
  53. Accelerator for Boosted Binary Features
  54. Accelerator for Spatio-Temporal Video Filtering
  55. Accelerators for object detection and tracking
  56. Accurate deep learning inference using computational memory
  57. Active-Set QP Solver on FPGA
  58. Adaptively Controlled Polarization And Hysteresis Curve Tracing For Polymer Piezoelectrics (1 S/B)
  59. Adding Linux Support to our DMA Engine (1-2S/B)
  60. Advanced 5G Repetition Combining
  61. Advanced Data Movers for Modern Neural Networks
  62. Advanced EEG glasses
  63. Advanced Physical Design: Reinforcement Learning for Macro Placement and Mix-Placer (B/1-2S)
  64. Adversarial Attacks Against Deep Neural Networks In Wearable Cameras
  65. Alias-Free Oscillator Synchronization for Arbitrary Waveforms
  66. Aliasing-Free Wavetable Music Synthesizer
  67. All-Digital In-Memory Processing
  68. All the flavours of FFT on MemPool (1-2S/B)
  69. Ambient RF Energy harvesting for Wireless Sensor Network
  70. An Efficient Compiler Backend for Snitch (1S/B)
  71. An Energy Efficient Brain-Computer Interface using Mr.Wolf
  72. An FPGA-Based Evaluation Platform for Mobile Communications
  73. An FPGA-Based Testbed for 3G Mobile Communications Receivers
  74. An Industrial-grade Bluetooth LE Mesh Network Solution
  75. An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
  76. An Ultra-Compact High-Power CMOS Power Amplifier for Millimeter-Wave 5G Communications
  77. An Ultra-Low-Power Neuromorphic Spiking Neuron Design
  78. An all Standard-Cell Based Energy Efficient HW Accelerator for DSP and Deep Learning Applications
  79. Analog
  80. AnalogInt
  81. Analog Compute-in-Memory Accelerator Interface and Integration
  82. Analog IC Design
  83. Analog Layout Engine
  84. Analog building blocks for mmWave manipulation
  85. Analysis and Design of Power Efficient RF/ mm-Wave LC-tank Oscillator in 28nm for 5G communication applications
  86. Analysis of Low-Power Wide Area Network Technologies for the Internet of Things
  87. Andrea Cossettini
  88. Andreas Kurth
  89. Android Software Design
  90. Android reliability governor
  91. Application Specific Frequency Synthesizers (Analog/Digital PLLs)
  92. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
  93. Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Training Strategy And Algorithmic optimizations
  94. Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
  95. Artificial Reverberation for Embedded Systems
  96. Assessment of novel photovoltaic architectures by circuit simulation
  97. Atretter
  98. Audio
  99. Audio DAC Conversion Jitter Measurement System
  100. Audio Signal Processing
  101. Audio Video Preprocessing In Parallel Ultra Low Power Platform
  102. Audio Visual Speech Recognition (1S/1M)
  103. Audio Visual Speech Separation (1S/1M)
  104. Audio Visual Speech Separation and Recognition (1S/1M)
  105. Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
  106. Autoencoder Accelerator for On-Chip Semi-Supervised Learning
  107. Automatic unplugging detection for Ultrasound probes
  108. Autonomous Mapping with Nano-Drones UWB and Novel Depth Sensors
  109. Autonomous Obstacle Avoidance with Nano-Drones and Novel Depth Sensors
  110. Autonomous Sensing For Trains In The IoT Era
  111. Autonomous Sensors For Underwater Monitoring In Smart Navy Systems
  112. Autonomous Smart Watches: Hardware and Software Desing
  113. Autonomous Smart Watches: Toward an ultra low power microphone detector with events classification
  114. Autonomus Drones With Novel Sensors And Ultra Wide Band
  115. BCI-controlled Drone
  116. BLISS - Battery-Less Identification System for Security
  117. Bandwidth Efficient NEureka
  118. Bandwidth Extension with Carrier Aggregation for Mobile Gigabit-Communication
  119. Baseband Meets CPU
  120. Baseband Processor Development for 4G IoT
  121. Bateryless Heart Rate Monitoring
  122. Battery indifferent wearable Ultrasound
  123. Beamspace processing for 5G mmWave massive MIMO on GPU
  124. Beat Cadence
  125. Beat DigRF
  126. Benchmarking a RISC-V-based Server on LLMs/Foundation Models (SA or MA)
  127. Benchmarking a heterogeneous 217-core MPSoC on HPC applications
  128. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S)
  129. Benchmarking a heterogeneous 217-core MPSoC on HPC applications (M/1-3S))
  130. Benjamin Sporrer
  131. Benjamin Weber
  132. BigPULP: Multicluster Synchronization Extensions
  133. BigPULP: Shared Virtual Memory Multicluster Extensions
  134. Big Data Analytics Benchmarks for Ara
  135. Biomedical Circuits, Systems, and Applications
  136. Biomedical System on Chips
  137. Biomedical Systems on Chip
  138. BirdGuard
  139. Birds Long Term Monitoring With Ultra Low Power Wireless Sensor Node
  140. Bluetooth Low Energy network with optimized data throughput
  141. Bluetooth Low Energy receiver in 65nm CMOS
  142. Bridging QuantLab with LPDNN
  143. Bringing XNOR-nets (ConvNets) to Silicon
  144. Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
  145. Brunn test
  146. Build the Fastest 2G Modem Ever
  147. Building an RTL top level for a Mempool-based Heterogeneous SoC (M/1-3S)
  148. CLIC for the CVA6
  149. CMOS power amplifier for field measurements in MRI systems
  150. CPS Software-Configurable State-Machine
  151. Cell-Free mmWave Massive MIMO Communication
  152. Cell Measurements for the 5G Internet of Things
  153. Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core
  154. Change-based Evaluation of Convolutional Neural Networks
  155. Channel Decoding for TD-HSPA
  156. Channel Estimation and Equalization for LTE Advanced
  157. Channel Estimation for 3GPP TD-SCDMA
  158. Channel Estimation for 5G Cellular IoT and Fast Fading Channels
  159. Channel Estimation for TD-HSPA
  160. Characterization of the susceptibility to cosmic radiation of wide bandgap power devices by radioactive sources and at cryogenic temperatures
  161. Characterization techniques for silicon photonics-Lumiphase
  162. Charge and heat transport through graphene nanoribbon based devices
  163. Charging System for Implantable Electronics
  164. Christoph Keller
  165. Christoph Leitner
  166. Circuits and Systems for Nanoelectrode Array Biosensors
  167. Classification of Evoked Local-Field Potentials in Rat Barrel Cortex using Hyper-dimensional Computing
  168. Coding Guidelines
  169. Coherence-Capable Write-Back L1 Data Cache for Ariane (M)
  170. Combining Multi Sensor Imaging and Machine Learning for Robust Far-Field Vision
  171. Combining Spiking Neural Networks with Hyperdimensional Computing for Autonomous Navigation
  172. Compiler Profiling and Optimizing
  173. Completed
  174. Compressed Sensing Reconstruction on FPGA
  175. Compressed Sensing for Wireless Biosignal Monitoring
  176. Compressed Sensing vs JPEG
  177. Compression of Ultrasound data on FPGA
  178. Compression of iEEG Data
  179. Computation of Phonon Bandstructure in III-V Nanostructures
  180. Configurable Ultra Low Power LDO
  181. Contextual Intelligence on Resource-constraint Bluetooth LE IoT Devices
  182. Continual Learning for Adaptive EEG Monitoring in Epileptic Seizure Detection
  183. Contrastive Learning for Self-supervised Clustering of iEEG Data for Epileptic Patients
  184. Control an external ADC using Programmable Real-Time Unit (PRU) Subsystem on Beaglebone Black used as embedded HPC-performance-monitoring device
  185. Convolution Neural Networks on our Ultra-Low Power Mult-Core Plattform PULP
  186. Counter-based Fast Power Estimation using FPGAs (M/1-3S)
  187. Covariant Feature Detector on Parallel Ultra Low Power Architecture
  188. Creating A Boundry Scan Generator (1-3S/B/2-3G)
  189. Creating A Reshuffling Mid-end For Reorganizing Data Inside The Compute Cluster (1-3S/B)
  190. Creating A Technology-independent USB1.0 Host Implementation Targetting ASICSs (1-3S/B)
  191. Creating a Compact Power Supply and Monitoring System for the Occamy Chip (1-3S/B/2-3G)
  192. Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)
  193. Creating a HDMI Video Interface for PULP
  194. Creating an At-memory Low-overhead Bufferless Matrix Transposition Accelerator (1-3S/B)
  195. Cryptography
  196. Cycle-Accurate Event-Based Simulation of Snitch Core
  197. DC-DC Buck converter in 65nm CMOS
  198. DMA Streaming Co-processor
  199. DaCe on Snitch
  200. Data Augmentation Techniques in Biosignal Classification
  201. Data Mapping for Unreliable Memories
  202. David J. Mack
  203. Deconvolution Accelerator for On-Chip Semi-Supervised Learning
  204. Deep-Learning Based Phoneme Recognition from a Ultra-Low Power Spiking Cochlea
  205. Deep Convolutional Autoencoder for iEEG Signals
  206. Deep Learning-based Global Local Planner for Autonomous Nano-drones
  207. Deep Learning Based Anomaly Detection in ECG Signals Using Foundation Models
  208. Deep Learning Projects
  209. Deep Learning for Brain-Computer Interface
  210. Deep Unfolding of Iterative Optimization Algorithms
  211. Deep neural networks for seizure detection
  212. Design-Space Exploration of Low-Resolution Matrix-Vector Multipliers
  213. Design Of A Biomarker Assay Based On Responsive Magnetic Nanoparticles
  214. Design Review
  215. Design and Evaluation of a Small Size Avalanche Beacon
  216. Design and Exploitation of a Test-Bench for Non-Destructive Characterization of the Susceptibility of Silicon Carbide (SiC) Power Devices to Cosmic Radiation
  217. Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors
  218. Design and Implementation of a Convolutional Neural Network Accelerator ASIC
  219. Design and Implementation of a Fully-digital Platform-independent Integrated Temperature Sensor Enabling DVFS in Open-source Tapeouts (1-3S/B)
  220. Design and Implementation of a multi-mode multi-master I2C peripheral
  221. Design and Implementation of an Approximate Floating Point Unit
  222. Design and Implementation of ultra low power vision system
  223. Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
  224. Design and implementation of the front-end for a portable ionizing radiation detector
  225. Design of Charge-Pump PLL in 22nm for 5G communication applications
  226. Design of MEMs Sensor Interface
  227. Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
  228. Design of Scalable Event-driven Neural-Recording Digital Interface
  229. Design of State Retentive Flip-Flops
  230. Design of Streaming Data Platform for High-Speed ADC Data
  231. Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
  232. Design of a 25 Gbps SerDes for optical chip-to-chip communication
  233. Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)
  234. Design of a D-Band Variable Gain Amplifier for 6G Communication
  235. Design of a Digital Audio Module for Ultra-Low Power Cellular Applications
  236. Design of a Fused Multiply Add Floating Point Unit
  237. Design of a High-​performance Hybrid PTZ for Multimodal Vision Systems
  238. Design of a Low Power Smart Sensing Multi-modal Vision Platform
  239. Design of a Prototype Chip with Interleaved Memory and Network-on-Chip
  240. Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
  241. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1-3S/B)
  242. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)
  243. Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (B/1-3S)
  244. Design of a VLIW processor architecture based on RISC-V
  245. Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
  246. Design of an Energy-Efficient Ethernet Interface for Linux-capable Systems
  247. Design of an LTE Module for the Internet of Things
  248. Design of an on-field adaptable pulse-processing unit for semicondutor radiation detectors
  249. Design of combined Ultrasound and Electromyography systems
  250. Design of combined Ultrasound and PPG systems
  251. Design of low-offset dynamic comparators
  252. Design of low mismatch DAC used for VAD
  253. Design space exploration of InP Heterojunction Bipolar Transistors (DHBTs)
  254. Design study of tunneling transistors based on a core/shell nanowire structures
  255. Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
  256. Designing a Power Management Unit for PULP SoCs
  257. Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)
  258. Desing and Implementation Of Long Lasting Key Finder With Bleetooth Low Energy
  259. Developing High Efficiency Batteries for Electric Cars
  260. Developing a Transposition Unit to Accelerate ML Workloads (1-3S/B)
  261. Developing a small portable neutron detector for detecting smuggled nuclear material
  262. Development Of A Test Bed For Ultrasonic Transducer Characterization (1 S/B)
  263. Development Of An FPGA-Based Optoacoustic Image Reconstruction Platform for Clinical Applications
  264. Development of a Rockfall Sensor Node
  265. Development of a fingertip blood pressure sensor
  266. Development of a syringe label reader for the neurocritical care unit
  267. Development of an efficient algorithm for quantum transport codes
  268. Development of an implantable Force sensor for orthopedic applications
  269. Development of statistics and contention monitoring unit for PULP
  270. Digital
  271. DigitalUltrasoundHead
  272. Digital Audio Interface for Smart Intensive Computing Triggering
  273. Digital Audio Processor for Cellular Applications
  274. Digital Beamforming for Ultrasound Imaging
  275. Digital Control of a DC/DC Buck Converter
  276. Digital Medical Ultrasound Imaging
  277. Digital Transmitter for Cellular IoT
  278. Digital Transmitter for Mobile Communications
  279. Digitally-Controlled Analog Subtractive Sound Synthesis
  280. EECIS
  281. EEG-based drowsiness detection
  282. EEG artifact detection for epilepsy monitoring
  283. EEG artifact detection with machine learning
  284. EEG earbud
  285. Edge Computing for Long-Term Wearable Biomedical Systems
  286. Efficient Banded Matrix Multiplication for Quantum Transport Simulations
  287. Efficient Execution of Transformers in RISC-V Vector Machines with Custom HW acceleration (M)
  288. Efficient Implementation of an Active-Set QP Solver for FPGAs
  289. Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
  290. Efficient NB-IoT Uplink Design
  291. Efficient Search Design for Hyperdimensional Computing
  292. Efficient Synchronization of Manycore Systems (M/1S)
  293. Efficient TNN Inference on PULP Systems
  294. Efficient TNN compression
  295. Efficient collective communications in FlooNoC (1M)
  296. Electrically verifying a CMOS Multi-Modal Electrochemical, Impedance, and Optical Cellular Sensing Array for Massively Paralleled Exoelectrogen Screening
  297. Electrothermal characterization of van der Waals Heterostructures with a partial overlap
  298. Elliptic Curve Accelerator for zkSNARKs
  299. Embedded Artificial Intelligence:Systems And Applications
  300. Embedded Audio Source Localization Exploiting Coincidence Detection in Asynchronous Spike Streams
  301. Embedded Gesture Recognition Using Novel Mini Radar Sensors
  302. Embedded Systems and autonomous UAVs
  303. Enabling Efficient Systolic Execution on MemPool (M)
  304. Enabling Standalone Operation
  305. Enabling Standalone Operation for a Mobile Health Platform
  306. Energy-Efficient Brain-Inspired Hyperdimensional Computing
  307. Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
  308. Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
  309. Energy Efficient AXI Interface to Serial Link Physical Layer
  310. Energy Efficient Autonomous UAVs
  311. Energy Efficient Circuits and IoT Systems Group
  312. Energy Efficient Serial Link
  313. Energy Efficient Smart Devices For Construction Building Maintenance Hilti Collaboration
  314. Energy Efficient SoCs
  315. Energy Neutral Multi Sensors Wearable Device
  316. Engineering For Kids
  317. Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)
  318. Enhancing our DMA Engine with Fault Tolerance
  319. Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
  320. EvaLTE: A 2G/3G/4G Cellular Transceiver FMC
  321. EvalEDGE: A 2G Cellular Transceiver FMC
  322. Evaluating An Ultra low Power Vision Node
  323. Evaluating SoA Post-Training Quantization Algorithms
  324. Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)
  325. Evaluating memory access pattern specializations in OoO, server-grade cores (M)
  326. Evaluating the RiscV Architecture
  327. Event-Driven Computing
  328. Event-Driven Convolutional Neural Network Modular Accelerator
  329. Event-Driven Vision on an embedded platform
  330. Event-based navigation on autonomous nano-drones
  331. Every individual on the planet should have a real chance to obtain personalized medical therapy
  332. Evolved EDGE Physical Layer Incremental Redundancy Architecture
  333. Experimental Validation of Impact Ionization Models for TCAD Simulation by a Novel Characterization Technique
  334. Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
  335. Exploration and Hardware Acceleration of Intra-Layer Mixed-Precision QNNs
  336. Exploratory Development of a Unified Foundational Model for Multi Biosignal Analysis
  337. Exploring Algorithms for Early Seizure Detection
  338. Exploring NAS spaces with C-BRED
  339. Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
  340. Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
  341. Exploring schedules for incremental and annealing quantization algorithms
  342. Extend the RI5CY core with priviledge extensions
  343. Extended Verification for Ara
  344. Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
  345. Extending our FPU with Internal High-Precision Accumulation (M)
  346. Extending the HERO RISC-V HPC stack to support multiple devices on heterogeneous SoCs (M/1-3S)
  347. Extending the RISCV backend of LLVM to support PULP Extensions
  348. Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
  349. Extreme-Edge Experience Replay for Keyword Spotting
  350. Eye movements
  351. Eye tracking
  352. Efficient Digital Signal Processing in High-Channel-Count High-Frame-Rate 3D Ultrasound Imaging Systems
  353. FFT-based Convolutional Network Accelerator
  354. FFT HDL Code Generator for Multi-Antenna mmWave Communication
  355. FPGA
  356. FPGA-Based Digital Frontend for 3G Receivers
  357. FPGA-based Implementation of a Novel Cell-Search Algorithm for Mobile Communications
  358. FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things
  359. FPGA Optimizations of Dense Binary Hyperdimensional Computing
  360. FPGA System Design for Computer Vision with Convolutional Neural Networks
  361. FPGA Testbed Implementation for Bluetooth Indoor Positioning
  362. FPGA acceleration of ultrasound computed tomography for in vivo tumor screening
  363. FPGA mapping of RPC DRAM
  364. Fabian Schuiki
  365. Fast Accelerator Context Switch for PULP
  366. Fast Simulation of Manycore Systems (1S)
  367. Fast Wakeup From Deep Sleep State
  368. Fast and Accurate Multiclass Inference for Brain–Computer Interfaces
  369. Fault-Tolerant Floating-Point Units (M)
  370. Fault Tolerance
  371. Feature Extraction and Architecture Clustering for Keyword Spotting (1S)
  372. Feature Extraction for Speech Recognition (1S)
  373. Feature Extraction with Binarized Descriptors: ASIC Implementation and FPGA Environment
  374. Federico Villani
  375. Ferroelectric Memristors for Artificial Neural Networks (IBM-Zurich)
  376. Final Presentation
  377. Final Report
  378. Finalizing and Releasing Our Open-source AXI4 IPs (1-3S/B/2-3G)
  379. Finite Element Simulations of Transistors for Quantum Computing
  380. Finite element modeling of electrochemical random access memory
  381. Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
  382. Flexfloat DL Training Framework
  383. Flexible Electronic Systems and Embedded Epidermal Devices
  384. Flexible Front-End Circuit for Biomedical Data Acquisition
  385. Floating-Point Divide & Square Root Unit for Transprecision
  386. Forward error-correction ASIC using GRAND
  387. Frank K. Gürkaynak
  388. Freedom from Interference in Heterogeneous COTS SoCs
  389. Full-band simulations of InP/GaAsSb/InP Double Heterojunction Bipolar Transistors (DHBTs)
  390. GDBTrace: A Post-Simulation Trace-Based RISC-V GDB Debugging Server (1S)
  391. GPT on the edge
  392. GRAND Hardware Implementation
  393. GSM Voice Capacity Evolution - VAMOS
  394. GUI-developement for an action-cam-based eye tracking device
  395. Glitches Reduce Listening Time of Your iPod
  396. Gomeza old project1
  397. Gomeza old project2
  398. Gomeza old project3
  399. Gomeza old project4
  400. Gomeza old project5
  401. Graph neural networks for epileptic seizure detection
  402. Guillaume Mocquard
  403. HERO: TLB Invalidation
  404. HW/SW Safety and Security
  405. Harald Kröll
  406. Hardware/software co-programming on the Parallella platform
  407. Hardware/software codesign neural decoding algorithm for “neural dust”
  408. Hardware Accelerated Derivative Pricing
  409. Hardware Acceleration
  410. Hardware Accelerator Integration into Embedded Linux
  411. Hardware Accelerator for Model Predictive Controller
  412. Hardware Accelerators for Lossless Quantized Deep Neural Networks
  413. Hardware Constrained Neural Architechture Search
  414. Hardware Exploration of Shared-Exponent MiniFloats (M)
  415. Hardware Support for IDE in Multicore Environment
  416. Heroino: Design of the next CORE-V Microcontroller
  417. Herschmi
  418. Heterogeneous SoCs
  419. High-Resolution, Calibrated Folding ADCs
  420. High-Resolution Large-Bandwidth Delta-Sigma A/D Converters in Ultra-Scaled CMOS
  421. High-Speed Digital-to-Analog Converter (DAC) for massive MIMO testing in 65nm CMOS
  422. High-Speed SAR ADC for next generation wireless communication in 12nm FinFET
  423. High-Throughput Authenticated Encryption Architectures based on Block Ciphers
  424. High-Throughput Hardware Implementations of Authenticated Encryption Algorithms
  425. High-speed Scene Labeling on FPGA
  426. High-throughput Embedded System For Neurotechnology in collaboration with INI
  427. High Performance Cellular Receivers in Very Advanced CMOS
  428. High Performance Digitally-Assisted Time Domain ADC Design for DPLL used in Cellular IOT
  429. High Performance SoCs
  430. High Power Efficient Digitally Controlled Oscillator Design for Cellular IOT
  431. High Speed FPGA Trigger Logic for Particle Physics Experiments
  432. High Throughput Turbo Decoder Design
  433. High performance continous-time Delta-Sigma ADC for biomedical applications
  434. High performance continuous-time Delta-Sigma ADC for magnetic resonance imaging
  435. High resolution, low power Sigma Delta ADC
  436. Huawei Research
  437. Human Intranet
  438. Hybrid Analog/Digital Leveling Loop for Very-Low-Distortion Oscillator
  439. Hyper-Dimensional Computing Based Predictive Maintenance
  440. Hyper Meccano: Acceleration of Hyperdimensional Computing
  441. Hyperdimensional Computing
  442. Hypervisor Extension for Ariane (M)
  443. IBM A2O Core
  444. IBM Research
  445. IBM Research–Zurich
  446. IP-Based SoC Generation and Configuration (1-3S)
  447. IP-Based SoC Generation and Configuration (1-3S/B)
  448. ISA extensions in the Snitch Processor for Signal Processing (1M)
  449. ISA extensions in the Snitch Processor for Signal Processing (M)
  450. Ibex: Bit-Manipulation Extension
  451. Ibex: FPGA Optimizations
  452. Ibex: Tightly-Coupled Accelerators and ISA Extensions
  453. IcySoC
  454. Image Sensor Interface and Pre-processing
  455. Image and Video Processing
  456. Implementation of Computationally Efficient Scattering Mechanisms for Periodic Devices and 2D Materials
  457. Implementation of a 2-D model for Li-ion batteries
  458. Implementation of a Cache Reliability Mechanism (1S/M)
  459. Implementation of a Coherent Application-Class Multicore System (1-2S)
  460. Implementation of a Heterogeneous System for Image Processing on an FPGA
  461. Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
  462. Implementation of a NB-IoT Positioning System
  463. Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
  464. Implementation of an AES Hardware Processing Engine (B/S)
  465. Implementation of an Accelerator for Retentive Networks (1-2S)
  466. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RI5CY core
  467. Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core
  468. Implementing A Low-Power Sensor Node Network
  469. Implementing Configurable Dual-Core Redundancy
  470. Implementing DSP Instructions in Banshee (1S)
  471. Implementing Hibernation on the ARM Cortex M0
  472. Improved Collision Avoidance for Nano-drones
  473. Improved Reacquisition for the 5G Cellular IoT
  474. Improved State Estimation on PULP-based Nano-UAVs
  475. Improving Cold-Start in Batteryless And Energy Harvesting Systems
  476. Improving Resiliency of Hyperdimensional Computing
  477. Improving Scene Labeling with Hyperspectral Data
  478. Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
  479. Improving datarate and efficiency of ultra low power wearable ultrasound
  480. Improving our Smart Camera System
  481. In-ear EEG signal acquisition
  482. Indoor Positioning with Bluetooth
  483. Indoor Smart Tracking of Hospital instrumentation
  484. Inductive Charging Circuit for Implantable Devices
  485. Influence of the Initial FilamentGeometry on the Forming Step in CBRAM
  486. Influence of the Initial Filament Geometry on the Forming Step in CBRAM
  487. Influence of the Initial Filament Geometry on the Forming Step in CBRAM.
  488. Infrared Wake Up Radio
  489. Integrated Devices, Electronics, And Systems
  490. Integrated Information Processing
  491. Integrated silicon photonic structures
  492. Integrated silicon photonic structures-Lumiphase
  493. Integrating Hardware Accelerators into Snitch
  494. Integrating Hardware Accelerators into Snitch (1S)
  495. Integrating Ultrasound Technology into a Fitness Tracking Device (1M, 2 B/S)
  496. Integrating an Open-Source Double-Precision Floating-Point DivSqrt Unit into CVFPU (1S)
  497. Integration Of A Smart Vision System
  498. Intelligent Power Management Unit (iPMU)
  499. Interfacing PULP with a Brain-Inspired Ultra-Low Power Spiking Cochlea
  500. Interference Cancellation for EC-GSM-IoT

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