View source for Successive Approximation Register (SAR) ADC

[[File:Successive Approximation Register DAC.png|thumb|400px]]
==Short Description==
Successive Approximation Register (SAR) ADCs are the architecture of choice for medium to high resolution low-power applications, such as battery powered systems. Their architecture consists of a front-end sample-and-hold (S/H), a comparator, a decision register, and a DAC. The ADC employs a binary search algorithm to perform the conversion. This project consists of building a MATLAB model, analyzing the different circuits of the ADC, and designing and implementing a high-resolution slowly clocked SAR converter. 

===Status: Available ===
: Looking for 1-2 Semester/Master students
: Contact: [[:User:Fateh | Schekeb Fateh]]
===Prerequisites===
: AIC
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===Status: Completed ===
: Fall Semester 2014 (sem13h2)
: Matthias Baer, Renzo Andri
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===Status: In Progress ===
: Student A, StudentB
: Supervision: [[:User:Belfanti | Sandro Belfanti]]
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===Character===
: 20% Theory
: 80% Circuit Design

===Professor===
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] --->
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] --->
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] --->
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] --->
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->

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==Detailed Task Description==

===Goals===
===Practical Details===
* '''[[Project Plan]]'''
* '''[[Project Meetings]]'''
* '''[[Design Review]]'''
* '''[[Coding Guidelines]]'''
* '''[[Final Report]]'''
* '''[[Final Presentation]]'''

==Results== 

==Links== 
[[Category:Analog]]
[[Category:Semester Thesis]]

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