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Revision as of 17:42, 16 January 2014

Creating Transmitter and Testbed Development for TD-SCDMA.jpg

Short Description

In this project you get the chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emerging from China. In order to complete the receiver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. The goal of this project is to design the transmitter and to develop a first testbed setup. The first step is to design the complete digital part of the transmitter. After the digital part has been implemented in VHDL and synthesized it can be tested on an FPGA board. You can then start to set up a testbed for your transmitter. The goal is to connect the FPGA board to the existing analog tranceiver to realize a standard compliant TD-HSPA transmitter. In the end, the complete chain will be able to transmit data from a PC through your digital part and the analog frontend over the air to a network analyzer.Note that this master project can be split up into two independent semester projects. The digital transmitter can also be realized during a VLSI design project and the testbed setup in another thesis.

Status: Available

Looking for 1-2 Semester/Master students
Contact: Sandro Belfanti

Prerequisities

VLSI I
MATLAB and VHDL is an advantage
Interest in Mobile Communications

Character

20% Theory/MATLAB
30% VHDL
50% Implementation

Professor

Qiuting Huang

Detailed Task Description

Goals

Practical Details

Results

Links