http://iis-projects.ee.ethz.ch/index.php?title=Ultra-High-Efficiency_Power_Supply_Management_for_Ultra-Low-Power_Systems_on_Chip&feed=atom&action=historyUltra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip - Revision history2024-03-28T11:33:41ZRevision history for this page on the wikiMediaWiki 1.28.0http://iis-projects.ee.ethz.ch/index.php?title=Ultra-High-Efficiency_Power_Supply_Management_for_Ultra-Low-Power_Systems_on_Chip&diff=890&oldid=prevKgf at 16:06, 3 February 20152015-02-03T16:06:46Z<p></p>
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</table>Kgfhttp://iis-projects.ee.ethz.ch/index.php?title=Ultra-High-Efficiency_Power_Supply_Management_for_Ultra-Low-Power_Systems_on_Chip&diff=849&oldid=prevKgf at 15:21, 14 January 20152015-01-14T15:21:35Z<p></p>
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<td colspan='2' style="background-color: white; color:black; text-align: center;">Revision as of 15:21, 14 January 2015</td>
</tr><tr><td colspan="2" class="diff-lineno" id="mw-diff-left-l8" >Line 8:</td>
<td colspan="2" class="diff-lineno">Line 8:</td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div># Unused units need to be fully shut down due to the leakage present even in absence of clock and signal transitions.</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div># Unused units need to be fully shut down due to the leakage present even in absence of clock and signal transitions.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'>−</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #ffe49c; vertical-align: top; white-space: pre-wrap;"><div>The goal of this Master Thesis is a power supply system offering several operation and biasing voltages that are all adjustable. Switching regulators are required in order to reduce voltage levels, theoretically <del class="diffchange diffchange-inline">lossess</del>. Due to parasitic elements, switching losses, and the supply currents of the controller, a careful design of each regulator is extremely important. A PCB-based system, containing of-the shelf converter chips where available, and discrete-component-based ( possibly uP or FPGA controlled) circuits where higher <del class="diffchange diffchange-inline">Efficiency </del>can be expected, is to be realized. This HW solution should also serve as evaluation platform for a later mixed-signal ASIC design.</div></td><td class='diff-marker'>+</td><td style="color:black; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #a3d3ff; vertical-align: top; white-space: pre-wrap;"><div>The goal of this Master Thesis is a power supply system offering several operation and biasing voltages that are all adjustable. Switching regulators are required in order to reduce voltage levels, theoretically <ins class="diffchange diffchange-inline">lossless</ins>. Due to parasitic elements, switching losses, and the supply currents of the controller, a careful design of each regulator is extremely important. A PCB-based system, containing of-the<ins class="diffchange diffchange-inline">-</ins>shelf converter chips where available, and discrete-component-based (possibly uP or FPGA controlled) circuits where higher <ins class="diffchange diffchange-inline">efficiency </ins>can be expected, is to be realized. This HW solution should also serve as evaluation platform for a later mixed-signal ASIC design.</div></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"></td></tr>
<tr><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td><td class='diff-marker'> </td><td style="background-color: #f9f9f9; color: #333333; font-size: 88%; border-style: solid; border-width: 1px 1px 1px 4px; border-radius: 0.33em; border-color: #e6e6e6; vertical-align: top; white-space: pre-wrap;"><div>===Status: Available ===</div></td></tr>
</table>Kgfhttp://iis-projects.ee.ethz.ch/index.php?title=Ultra-High-Efficiency_Power_Supply_Management_for_Ultra-Low-Power_Systems_on_Chip&diff=845&oldid=prevKgf: Created page with "500px ==Short Description== In our research group, Systems on Chip (SoC) with the lowest possible 'energy per operation' are developed..."2015-01-14T13:54:56Z<p>Created page with "<a href="/index.php?title=File:Pulp_Efficient_Supply.jpg" title="File:Pulp Efficient Supply.jpg">thumb|500px</a> ==Short Description== In our research group, Systems on Chip (SoC) with the lowest possible 'energy per operation' are developed..."</p>
<p><b>New page</b></p><div>[[File:Pulp Efficient Supply.jpg|thumb|500px]]<br />
==Short Description==<br />
In our research group, Systems on Chip (SoC) with the lowest possible 'energy per operation' are developed ([[PULP]]). Such an effort is useless if a power supply with low efficiency adds significant losses. As important as a high-efficiency is controllability: lowest energy consumption in VLSI chips requires several dynamically adaptable voltages: <br />
<br />
# The power dissipation of a digital circuit is proportional to the squared supply voltage. Reducing it to the lowest possible value saves energy! <br />
# Individual voltages for different sub-circuits allow further savings. <br />
# The power dissipation is also proportional to the frequency. At low frequencies, the leakage currents start to be dominant. They can be reduced by adjusting the body bias voltage. <br />
# Unused units need to be fully shut down due to the leakage present even in absence of clock and signal transitions.<br />
<br />
The goal of this Master Thesis is a power supply system offering several operation and biasing voltages that are all adjustable. Switching regulators are required in order to reduce voltage levels, theoretically lossess. Due to parasitic elements, switching losses, and the supply currents of the controller, a careful design of each regulator is extremely important. A PCB-based system, containing of-the shelf converter chips where available, and discrete-component-based ( possibly uP or FPGA controlled) circuits where higher Efficiency can be expected, is to be realized. This HW solution should also serve as evaluation platform for a later mixed-signal ASIC design.<br />
<br />
===Status: Available ===<br />
: Looking for 1-2 Master students<br />
: Contact: [[:User:Felber | Norbert Felber]]<br />
===Prerequisites===<br />
: Some experience in circuit design with discrete active and passive components.<br />
: Interest in low-current power converters.<br />
: Preferably knowledge of analog IC design.<br />
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: Fall Semester 2014 (sem13h2)<br />
: Matthias Baer, Renzo Andri<br />
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===Character===<br />
: 30% Theory<br />
: 50-60% Circuit design and measurement<br />
: 20-10% IC design <br />
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===Professor===<br />
: [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini]<br />
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==Detailed Task Description==<br />
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===Goals===<br />
===Practical Details===<br />
* '''[[Project Plan]]'''<br />
* '''[[Project Meetings]]'''<br />
* '''[[Design Review]]'''<br />
* '''[[Coding Guidelines]]'''<br />
* '''[[Final Report]]'''<br />
* '''[[Final Presentation]]'''<br />
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==Results== <br />
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[[Category:Digital]]<br />
[[Category:Available]]<br />
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