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Ultra-High-Efficiency Power Supply Management for Ultra-Low-Power Systems on Chip

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Short Description

In our research group, Systems on Chip (SoC) with the lowest possible 'energy per operation' are developed (PULP). Such an effort is useless if a power supply with low efficiency adds significant losses. As important as a high-efficiency is controllability: lowest energy consumption in VLSI chips requires several dynamically adaptable voltages:

  1. The power dissipation of a digital circuit is proportional to the squared supply voltage. Reducing it to the lowest possible value saves energy!
  2. Individual voltages for different sub-circuits allow further savings.
  3. The power dissipation is also proportional to the frequency. At low frequencies, the leakage currents start to be dominant. They can be reduced by adjusting the body bias voltage.
  4. Unused units need to be fully shut down due to the leakage present even in absence of clock and signal transitions.

The goal of this Master Thesis is a power supply system offering several operation and biasing voltages that are all adjustable. Switching regulators are required in order to reduce voltage levels, theoretically lossless. Due to parasitic elements, switching losses, and the supply currents of the controller, a careful design of each regulator is extremely important. A PCB-based system, containing of-the-shelf converter chips where available, and discrete-component-based (possibly uP or FPGA controlled) circuits where higher efficiency can be expected, is to be realized. This HW solution should also serve as evaluation platform for a later mixed-signal ASIC design.

Status: Available

Looking for 1-2 Master students
Contact: Norbert Felber

Prerequisites

Some experience in circuit design with discrete active and passive components.
Interest in low-current power converters.
Preferably knowledge of analog IC design.

Character

30% Theory
50-60% Circuit design and measurement
20-10% IC design

Professor

Luca Benini

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