Difference between revisions of "User:Matheusd"
From iis-projects
(→Available Projects) |
|||
| Line 17: | Line 17: | ||
</DynamicPageList> | </DynamicPageList> | ||
| − | + | ==Projects In Progress== | |
<DynamicPageList> | <DynamicPageList> | ||
category = In progress | category = In progress | ||
| Line 23: | Line 23: | ||
</DynamicPageList> | </DynamicPageList> | ||
| − | + | ==Completed Projects== | |
<DynamicPageList> | <DynamicPageList> | ||
category = Completed | category = Completed | ||
Revision as of 14:43, 29 October 2020
Contents
Matheus Cavalcante
- e-mail: matheusd@iis.ee.ethz.ch
Interests
- Computer and System Architecture
- High Performance Computing
- Vector Processing
- Interconnection Networks
Available Projects
- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M)
- Fast Simulation of Manycore Systems (1S)
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
Projects In Progress
No pages meet these criteria.
Completed Projects
- Spatz grows wings: Physical Implementation of a Vector-Powered Manycore System (2S)
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Transforming MemPool into a CGRA (M)
- Physical Implementation of Ara, PULP's Vector Machine (1-2S)
- Physical Implementation of MemPool, PULP's Manycore System (1M/1-2S)
- Manycore System on FPGA (M/S/G)
- PULP in space - Fault Tolerant PULP System for Critical Space Applications
- ISA extensions in the Snitch Processor for Signal Processing (M)
- MemPool on HERO (1S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- Ara: Update PULP's Vector Processor with the recent RISC-V Vector Extension Development
