Revision as of 13:39, 20 October 2020

Paul Scheffler

I received my B.Sc. and M.Sc in electrical engineering from ETH Zürich in 2018 and 2020, respectively, where I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Luca Benini.

My current research interests include

• Energy-efficient high-performance SoCs
• Manycore systems
• Sparse computing.

If any of these sound interesting to you, do not hesitate to contact me or come by my office!

Contact

Projects

Available Projects

• Scaleout Study on Interleaved Memory Transfers in Huge Manycore Systems with Multiple HBM Channels (M/1-3S)
• Accelerating Stencil Workloads on Snitch using ISSRs (1-2S/B)
• An Efficient Compiler Backend for Snitch (1S/B)
• Towards Formal Verification of the iDMA Engine (1-3S/B)
• Evaluating memory access pattern specializations in OoO, server-grade cores (M)
• IP-Based SoC Generation and Configuration (1-3S/B)

Projects In Progress

No pages meet these criteria.

Completed Projects

• Improving SystemVerilog Support for Free And Open-Source EDA Tools (1-3S/B)
• Extension and Evaluation of TinyDMA (1-2S/B/2-3G)
• Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)
• Augmenting Our IPs with AXI Stream Extensions (M/1-2S)
• Implementing DSP Instructions in Banshee (1S)
• Streaming Integer Extensions for Snitch (M/1-2S)
• A Unified Compute Kernel Library for Snitch (1-2S)
• Enhancing our DMA Engine with Vector Processing Capabilities (1-2S/B)
• Efficient Memory Stream Handling in RISC-V-based Systems (M/1-2S)
• Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
• LLVM and DaCe for Snitch (1-2S)
• Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
• An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
• A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
• A Flexible Peripheral System for High-Performance Systems on Chip (M)
• A Snitch-based Compute Accelerator for HERO (M/1-2S)