Difference between revisions of "User:Paulsc"
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| + | =Paul Scheffler= | ||
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| + | [[File:Paulsc_face_1to1.png|thumb|200px|]] | ||
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| + | I received my B.Sc. and M.Sc in electrical engineering from ETH Zürich in 2018 and 2020, respectively, where I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Luca Benini. | ||
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| + | My current research interests include | ||
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| + | * Energy-efficient high-performance SoCs | ||
| + | * Manycore systems | ||
| + | * Sparse computing. | ||
| + | |||
| + | If any of these sound interesting to you, do not hesitate to contact me or come by my office! | ||
| + | |||
| + | ==Contact== | ||
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| + | |||
==Projects== | ==Projects== | ||
Revision as of 13:39, 20 October 2020
Contents
Paul Scheffler
I received my B.Sc. and M.Sc in electrical engineering from ETH Zürich in 2018 and 2020, respectively, where I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Luca Benini.
My current research interests include
- Energy-efficient high-performance SoCs
- Manycore systems
- Sparse computing.
If any of these sound interesting to you, do not hesitate to contact me or come by my office!
Contact
Projects
Available Projects
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- RISC-V base ISA for ultra-low-area cores (2-3G)
- IP-Based SoC Generation and Configuration (1-3S/B)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
Projects In Progress
- LLVM and DaCe for Snitch (1-2S)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
