User:Paulsc
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Paul Scheffler
I received my B.Sc. and M.Sc in electrical engineering from ETH Zürich in 2018 and 2020, respectively, where I am currently pursuing a Ph.D. degree under the Digital Circuits and Systems group of Prof. Luca Benini.
My current research interests include
- Energy-efficient high-performance SoCs
- Manycore systems
- Sparse computing.
If any of these sound interesting to you, do not hesitate to contact me or come by my office! We are always looking for motivated students and interesting ideas. You can find some currently available projects below.
Contact
- e-mail: paulsc@iis.ee.ethz.ch
- phone: +41 44 632 09 15
- office: ETZ J85
Projects
Available Projects
- Evaluating memory access pattern specializations in OoO, server-grade cores (M)
- IP-Based SoC Generation and Configuration (1-3S/B)
- RISC-V base ISA for ultra-low-area cores (2-3G)
- SystemVerilog formatter for our LowRISC-based guidelines (2-3G)
Projects In Progress
- LLVM and DaCe for Snitch (1-2S)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- An RPC DRAM Implementation for Energy-Efficient ASICs (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
