Pasquale Davide Schiavone
Pasquale Davide Schiavone is a PhD student at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group led by Prof. Luca Benini. He obtained a BSc. and a MSc. from "Politecnico di Torino" in computer engineering in 2013 and 2016 respectively. His main research focus is on low-power energy-efficient computer architectures for Internet-Of-Things systems and brain-machine interfaces through EEG and neural action potential signals.
From January to June 2018 I visited the Centre of Bio-Inspired Technology at Imperial College London in the Next Generation Neural Interfaces group.
- Computer and System Architecture
- Digital ASIC Design
- Embedded systems
- Heterogeneous multicore architectures for energy-efficient and low-power embedded systems
- Brain-Machine interface
- Implementation of the RISC-V Bit Manipulation (RVB) extensions for our RISC-V core (semester/master thesis)
- Arnold: Developing efficient IoT data processing applications for a versatile PULPissimo-based SoC in 22nm FDSOI (semester/master thesis)
- Cerebellum: Design of a Programmable Smart-Peripheral for the Ariane Core (semester/master thesis)
- Design of Scalable Event-driven Neural-Recording Digital Interface (semester/master thesis)
- Hardware Accelerators for Lossless Quantized Deep Neural Networks (semester/master thesis)
- If you have your personal idea, you can also contact me for projects!
RISC-V is an open-source Instruction Set Architecture (ISA) governed by the no-profit organization RISC-V (https://riscv.org/). Thanks to its simplicity, efficiency and free to use nature, in the last years it has been heavily adopted by industries for products, evaluation board as well as by university for vehicle to research project. Interesting examples are products coming from companies like NXP with the Vega board (https://hackaday.com/2019/02/04/openisa-launches-free-risc-v-vegaboard/), GAP8 from GreenWaves (https://greenwaves-technologies.com/ai_processor_gap8/), SiFive core IPs (https://www.sifive.com/risc-v-core-ip) or Dolphin Integration with the Tornado board (https://www.design-reuse.com/news/44159/dolphin-integration-risc-v-subsystem.html) and many more. ETH and in particular our Digital Circuits and Systems group at IIS contributed to the open-source RISC-V community by providing three cores RI5CY, zero-riscy and Ariane that have been also used in aforementioned products. Moreover, they have been recently graduated from academic-level IP quality to industry with the support of big companies like Google, SiLabs, NXP, etc. One of the key success point of RISC-V along its free and open architecture is its extendability. Among the official instruction extensions, some of the ISA encoding space is left to implement custom instructions that face custom optimization that vary from context to context. Under the PULP project here in our group (https://pulp-platform.org/), the RI5CY has been extended with custom instructions to support signal processing, bit manipulation tasks, hardware-loops and so on. Some of the extensions are also organized inside RISC-V to be discussed in task-groups among members of the foundation. For instance, there are task groups to specify Vector extensions (RVV), Packed SIMD extensions (RVP), Bit Manipulation (RVB) etc. Recently, the RISC-V community has proposed a quite stable proposal for the RVB instructions https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf. Some of those are indeed very similar to the one developed for the PULP project and some are not. Some are missing and some are not present part of the PULP extensions.
We propose a semester thesis to implement the proposed RVB extensions to the RI5CY core. Such tasks requires to:
- Replace the ones that are similar/equal
- Implement the missing ones
- Evaluate the impact in AREA and Timing with a detailed report
- Evaluate the impact in performance/execution time for a given set of benchmarks
In case of a master thesis, this work will be further investigated for the 64 bit RISC-V core Ariane, plus enhancement on the RI5CY verification strategy and execution trace.
To work on this project, you will need:
- to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL) - having followed the VLSI1 class or equivalent is mandatory, VLSI2 course recommended
- to have prior knowledge in assembler/C program language
Other skills that you might find useful include:
- to be strongly motivated for a difficult but super-cool project
If you want to work on this project, but you think that you do not match some the required skills, we can give you some preliminary exercise to help you fill in the gap.
- Deep Learning for Brain-Computer Interface (semester thesis)
- Office: J89
- e-mail: firstname.lastname@example.org